Low-Power High-Speed Double Gate 1-bit Full Adder Cell
Abstract
In this paper, we proposed an efficient full adder circuit using 16 transistors. The proposed high-speed adder circuit able to operate at very low voltage and maintain the proper output voltage swing and also balanced the power consumption and speed. Proposed design is based on CMOS mixed threshold voltage logic (MTVL) and implemented in 180nm CMOS technology). In the proposed technique the most time-consuming and power consuming XOR gates and multiplexor are designed using MTVL scheme. The maximum average power consumed by the proposed circuit is 6.94µW at 1.8V supply voltage and frequency of 500 MHz, which is less than other conventional methods. Power, delay, and area are optimized by using pass transistor logic and verified using SPICE simulation tool at desired broad frequency range. It is also observed that the proposed designs successfully utilized in many cases, especially whenever the lowest power consumption and delay are aimed.
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R. Zimmermann and W. Fichtner, “Low-Power Logic Styles: CMOS versus Pass-Transistor Logic”, IEEE Journal of Solid-State Circuits, Vol. 32, 1997.
G. Hang and X. Wu, “Improved structure for adiabatic CMOS circuits design”, Microelectronics Journal, vol. 33, pp. 403–407, 2002.
J.-F. Lin, Y.-T. Hwang, M.-H. Sheu, C.-C. Ho, “A Novel High-Speed and Energy Efficient 10-Transistor Full Adder”, IEEE Transactions on Circuits and Systems-I, Vol. 54, 2007.
S.-M. Kang, Y. Leblebici, “CMOS digital integrated circuits”, Tata McGraw-Hill Education, 2003.
N. H. Weste and K. Eshraghian, “Principles of CMOS VLSI design”, Vol. 188, Addison-Wesley New York, 1985.
S. Yuan, Y. Li, Y. Yuan, Y. Liu, “Pass transistor with dual threshold voltage domino logic design using standby switch for reduced subthreshold leakage current”, Microelectronics Journal, vol. 44, pp. 1099–1106, 2013.
N. Zhuang and H. Wu, “A new design of the CMOS full adder”, IEEE journal of solid-state circuits, vol. 27, pp. 840–844, 1992.
R. Shalem, E. John, and E. John, “A novel low power energy recovery full adder cell, in: VLSI, Proceedings. Ninth Great Lakes Symposium on, IEEE, pp. 380–383, 1999.
H. T. Bui, Y. Wang and Y. Jiang, “Design and analysis of low-power 10-transistor full adders using novel xor-xnor gates”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 49, pp. 25-30, 2002.
R. Kumar, S. Roy, A. Bhattacharyya, An efficient low power 1-bit full adder using multi-threshold voltage scheme, in: Proc.of Int. Conf. on Advancement of Computer Communication and Electrical Technology, CRC, Taylor & Francis Group, pp. 93-97, 2016.
S. Abbasalizadeh, B. Forouzandeh, Full adder design with gdi cell and independent double gate transistor, in: Electrical Engineering (ICEE), 2012 20th Iranian Conference on, IEEE, 2012, pp. 130–134.
K. Navi, V. Foroutan, M. R. Azghadi, M. Maeen, M. Ebrahimpour, M. Kaveh and O. Kavehei, “A novel low-power full-adder cell with new technique in designing logical gates based on static cmos inverter”, Microelectronics Journal, vol. 40, pp. 1441–1448, 2009.
Y. Jiang, A. Al-Sheraidah, Y. Wang, E. Sha and J.-G. Chung, “A novel multiplexer-based low-power full adder”, Circuits and Systems II: Express Briefs, IEEE Transactions on, vol. 51, pp. 345–348, 2004.
T. T. Jeong, ‘Implementation of low power adder design and analysis based on power reduction technique”, Microelectronics Journal, vol. 39, pp. 1880–1886, 2008.
M. Alioto and G. Palumbo, “Analysis and comparison on full adder block in submicron technology’, Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, vol. 10, pp. 806–823, 2002.
A. M. Shams and M. A. Bayoumi, “A novel high-performance CMOS 1-bit full-adder cell”, Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 47, pp. 478–481, 2000.
V. Sundararajan, K. K. Parhi, Low power synthesis of dual threshold voltage CMOS VLSI circuits, in: Proceedings of the 1999 international symposium on Low power electronics and design, ACM, pp. 139–144, 1999.
C. Senthilpari, A. K. Singh and K. Diwakar, “Design of a low-power high performance, 8*8bit multiplier using a shannon-based adder cell”, Microelectronics Journal, vol. 39, pp. 812–821, 2008.
H. Pettenghi, M. J. Avedillo and J. M. Quintana, “Using multi-threshold threshold gates in rtd-based logic design: A case study”, Microelectronics Journal, vol. 39, pp. 241–247, 2008.
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