High-Performance Ternary (4:2) Compressor Based on Capacitive Threshold Logic

Reza Faghih Mirzaee, Akram Reza

Abstract


This paper presents a ternary (4:2) compressor, which is an important component in multiplication. However, the structure differs from the binary counterpart since the ternary model does not require carry signals. The method of capacitive threshold logic (CTL) is used to achieve the output signals directly. Unlike the previously presented similar structure, the entire capacitor network is divided into two parts. This segregation results in higher reliability and robustness against unwanted process, voltage, and temperature (PVT) variations. Simulations are performed by HSPICE and 32nm CNFET technology. Simulation results demonstrate about 94% higher performance in terms of power-delay product (PDP) for the new design over the previous one.

Full Text:

PDF

References


G. Jaberipur and M. Ghodsi, “High radix signed digit number systems: representation paradigms”, Scientia Iranica, vol. 10, no. 4, pp. 383-391, 2003.

E. Dubrova, “Multiple-valued logic in VLSI: challenges and opportunities”, Proceedings of NORCHIP’99, pp. 340-350, 1999.

S.L. Hurst, “Multiple-valued logic, its status and its future”, IEEE Transactions on Computers, vol. C-33, no. 12, pp. 1160-1179, 1984, DOI: 10.1109/TC.1984.1676392.

S.K. Hsu, S.K. Mathew, M.A. Anders, B.R. Zeydel, V.G. Oklobdzija, R.K. Krishnamurthy, and S.Y. Borkar, “A 110 GOPS/W 16-bit multiplier and reconfigurable PLA loop in 90-nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 256-264, 2006, DOI: 10.1109/JSSC.2005.859893.

M.E. Kaihara and N. Takagi, (2008). “Bipartite modular multiplication method”, IEEE Transactions on Computers, vol. 57, no. 2, pp. 157-164, 2008, DOI: 10.1109/TC.2007.70793.

J. Gu, and C.-H. Chang, “Ultra low voltage, low power 4-2 compressor for high speed multiplications”, Proceedings of the International Symposium on Circuits and Systems, 5, pp. 321-324, 2003, DOI: 10.1109/ISCAS.2003.1206267.

A. Pishvaie, G. Jaberipur, and A. Jahanian, “Improved CMOS (4; 2) compressor designs for parallel multipliers”, Computers and Electrical Engineering, vol. 38, no. 6, pp. 1703-1716, 2012, DOI: 10.1016/j.compeleceng.2012.07.015.

H. Ozdemir, A. KepKep, B. Pamir, Y. Leblebici, and U. Cilingiroglu, “A capacitive threshold-logic gate”, IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1141-1150, 1996, DOI: 10.1109/4.508261.

V. Beiu, J.M. Quintana, and M.J. Avedillo, “VLSI implementations of threshold logic-a comprehensive survey”, IEEE Transactions on Neural Networks, vol. 14, no. 5, pp. 1217-1243, 2003, DOI: 10.1109/TNN.2003.816365.

A. Stokman, “Implementation of threshold logic”, M.Sc. Thesis, Delft University of Technology, 1998.

R. Faghih Mirzaee, M.H. Moaiyeri, M. Maleknejad, K. Navi, and O. Hashemipour, “Dramatically low-transistor-count high-speed ternary adders”, IEEE 43rd International Symposium on Multiple-Valued Logic, pp. 170-175, 2013, DOI: 10.1109/ISMVL.2013.24.

R. Faghih Mirzaee and K. Navi, “Optimized adder cells for ternary ripple-carry addition”, IEICE Transactions on Information and systems, vol. E97-D, no. 9, pp. 2312-2319, 2014, DOI: 10.1587/transinf.2013LOP0007.

S. Tabrizchi, H. Sharifi, F. Sharifi, and K. Navi, “A novel design approach for ternary compressor cells based on CNTFETs”, Circuits, Systems, and Signal Processing, vol. 35, no. 9, pp. 3310-3322, 2016, DOI: 10.1007/s00034-015-0197-z.

A. Raychowdhury and K. Roy, “Carbon nanotube electronics: design of high-performance and low-power digital circuits”, IEEE Transactions on Circuits and Systems I, vol. 54, no. 11, pp. 2391-2401, 2007, DOI: 10.1109/TCSI.2007.907799.

J. Appenzeller, “Carbon nanotube for high-performance electronics-progress and prospect”, Proceedings of IEEE, vol. 96, no. 2, pp. 201-211, 2008, DOI: 10.1109/JPROC.2007.911051.

A. Rahman, I. Guo, S. Datta, and M.S. Lundstrom, “Theory of ballistic nanotransistors”, IEEE Transactions on Electron Devices, vol. 50, no. 9, pp. 1853-1864, 2003, DOI: 10.1109/TED.2003.815366.

S. Mehrabi, R. Faghih Mirzaee, S. Zamanzadeh, and A. Jamalian, “A new 16-bit×16-bit multiplier architecture by m:2 and m:3 compressors”, International Journal of Information and Electronics Engineering, vol. 6, no. 2, pp. 79-83, 2016, DOI: 10.18178/IJIEE.2016.6.2.599.

R. Faghih Mirzaee, K. Navi, and N. Bagherzadeh, “High-efficient circuits for ternary addition”, VLSI Design, vol. 2014, article ID 534587, pp. 1-15, 2014, DOI: 10.1155/2014/534587.

D.R. Haring, “Multi-threshold threshold elements”, IEEE Transactions on Electronic Computers, vol. EC-15, no. 1, pp. 45-65, 1966, DOI: 10.1109/PGEC.1966.264375.

J. Deng, “Device modeling and circuit performance evaluation for nanoscale devices: Silicon technology beyond 45 nm node and carbon nanotube field effect transistors”, Ph.D. Thesis, Stanford University, 2007.

N. Maleknejad, R. Faghih Mirzaee, K. Navi, and A. Dargahi, “A systematic approach to design Boolean functions using CNFETs and an array of CNFET capacitors”, Journal of Circuits, Systems, and Computers, vol. 23, no. 3, pp. 1-35, 2014, DOI: 10.1142/S0218126614500352.

Y.B. Kim and Y.-B. Kim, “High speed and low-power transceiver design with CNFET and CNT bundle interconnect”, IEEE International SOC Conference, pp. 152-157, 2010, DOI: 10.1109/SOCC.2010.5784733.

J.L. Garcia, J.F. Ramos, and A.G. Bohorquez, “A balanced capacitive threshold logic gate”, Analog Integrated Circuits and Signal Processing, vol. 40, no. 1, pp. 61-69, 2004, DOI: 10.1023/B:ALOG.0000031434.48142.a3.

Stanford University CNFET Model website, 2008, Available at: https://nano.stanford.edu/model.php.

S. Director, and G. Hachtel, “The simplicial approximation approach to design centering”, IEEE Transactions on Circuits and Systems, vol. 24, no. 7, pp. 363-372, 1977, DOI: 10.1109/TCS.1977.1084353.

K. El Shabrawy, K. Maharatna, D. Bagnall, and B.M. Al-Hashimi, “Modeling SWCNT bandgap and effective mass variation using a Monte Carlo approach”, IEEE Transactions on Nanotechnology, vol. 9, no. 2, pp. 184-193, 2010, DOI: 10.1109/TNANO.2009.2028343.

H. Shahidipour, A. Ahmadi, and K. Maharatna, “Effect of variability in SWCNT-based logic gates”, Proceedings of 12th International Symposium on Integrated Circuits, pp. 252-255, 2009.


Refbacks

  • There are currently no refbacks.


International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences

eISSN: 2300-1933