Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold

Shruti Kalra, Amalendu Bhattacharyya


Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as
the application of the proposed model.

Full Text:



Dreslinski, Ronald G., Michael Wieckowski, David Blaauw, Dennis Sylvester, and Trevor Mudge. ”Near-threshold computing: Reclaiming moore’s law through energy efficient integrated circuits.” Proceedings of the IEEE 98, no. 2 (2010): 253-266.

Markovic, Dejan, Cheng C. Wang, Louis P. Alarcon, Tsung-Te Liu, and Jan M. Rabaey. ”Ultralow-power design in near-threshold region.” Proceedings of the IEEE 98, no. 2 (2010): 237-252.

Enz, Christian C., and Eric A. Vittoz. Charge-based MOS transistor modeling: the EKV model for low-power and RF IC design. John Wiley & Sons, 2006.

Keller, Sean, David Money Harris, and Alain J. Martin. ”A compact transregional model for digital CMOS circuits operating near threshold.” Very Large Scale Integration (VLSI) Systems, IEEE Transactions on 22, no. 10 (2014): 2041-2053.

Kaul, Himanshu, Mark Anders, Steven Hsu, Amit Agarwal, Ram

Krishnamurthy, and Shekhar Borkar. ”Near-threshold voltage (NTV) design: opportunities and challenges.” In Proceedings of the 49th Annual Design Automation Conference, pp. 1153-1158. ACM, 2012.

Chen, Gregory, Dennis Sylvester, David Blaauw, and Trevor Mudge. ”Yield-driven near-threshold SRAM design.” IEEE transactions on very large scale integration (VLSI) systems 18, no. 11 (2010): 1590-1598.

Calhoun, Benton H., Alice Wang, and Anantha Chandrakasan. ”Modeling and sizing for minimum energy operation in subthreshold circuits.” IEEE Journal of Solid-State Circuits 40, no. 9 (2005): 1778-1786.

Alioto, Massimo. ”Ultra-low power VLSI circuit design demystified and explained: A tutorial.” IEEE Transactions on Circuits and Systems I: Regular Papers 59, no. 1 (2012): 3-29.

Gonzalez, Ricardo, Benjamin M. Gordon, and Mark A. Horowitz.

”Supply and threshold voltage scaling for low power CMOS.” IEEE

Journal of Solid-State Circuits 32, no. 8 (1997): 1210-1216.

Taur, Yuan. ”CMOS design near the limit of scaling.” IBM Journal of Research and Development 46, no. 2.3 (2002): 213-222.

Chen, Poki, et al. ”A time-to-digital-converter-based CMOS smart temperature sensor.” IEEE Journal of Solid-State Circuits 40.8 (2005): 1642-1648.

Kalra, Shruti, et al. ”An Analytical Study Of Temperature Dependence of Scaled CMOS Digital Circuits Using a-Power MOSFET Model” Journal of Integrated Circuits and Systems 11.1 (2016): 57-68.


  • There are currently no refbacks.

International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences

eISSN: 2300-1933