On and Off Chip Capacitor Free, Fast Response, Low Drop-out Voltage Regulator

Guru Prasad, Kumara Shama


A low drop-out [LDO] voltage regulator with fast
transient response which does not require capacitor for proper
operation is proposed in this paper. Recent cap-less LDOs do
not use off chip capacitor but instead they use on chip capacitor
which occupy large area on chip. In the proposed LDO this on
chip capacitor is also avoided. A novel secondary local feed-back
technique is introduced which helps to achieve a good transient
response even in the absence of output capacitor. Further a
self compensating error amplifier is selected to eliminate the
need of compensating capacitor. Stability analysis shows that the
proposed LDO is stable with a phase margin of 78 0 . The proposed
LDO is laid out using Cadence spectre in 180 nm standard CMOS
technology. Post layout simulation is carried out and LDO gives
6mV/V and 360μV /mA line and load regulation respectively. An
undershoot of 120 mV is observed during the load transition
from 0 mA to 50 mA with 1 μs transition time, however LDO is
able to recover within 1.4μs. Since capacitor is not required in
any part of design, it occupies only 0.010824 mmXmm area on chip.

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Y. Zeng, Y. Li, X. Zhang, and H.-z. Tan, “A push-pulled fvf based output-

capacitorless ldo with adaptive power transistors,” Microelectronics

Journal, vol. 64, pp. 69–77, 2017.

A. Saberkari, E. Alarcón, and S. B. Shokouhi, “Fast transient current-

steering cmos ldo regulator based on current feedback amplifier,” Inte-

gration, the VLSI Journal, vol. 46, no. 2, pp. 165–171, 2013.

J. Hinojo, C. Luján-Martı́nez, A. Torralba, and J. Ramı́rez-Angulo,

“Internally compensated ldo regulator based on the cascoded fvf,”

Microelectronics Journal, vol. 45, no. 10, pp. 1268–1274, 2014.

S.-K. Kao, Y.-Z. Lee, C.-Y. Ku, and H.-C. Cheng, “Output capacitor-

free low-dropout regulator with fast transient response and ultra small

compensation capacitor,” Microelectronics Journal, vol. 56, pp. 134–

, 2016.

X. Ming, N. Li, X.-m. Zhang, Y. Lu, Z.-k. Zhou, and Z. Wang, “A

capacitor-less ldo regulator with dynamic transconductance enhancement

technique,” Analog Integrated Circuits and Signal Processing, vol. 84,

no. 3, pp. 433–444, 2015.

J. Yeo, K. Javed, J. Lee, J. Roh, and J.-D. Park, “A capacitorless low-

dropout regulator with enhanced slew rate and 4.5ua quiescent current,”

Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp.

–235, 2017.

Y. Yosef-Hay, D. Ø. Larsen, P. L. Muntal, and I. H. Jørgensen, “Fully

integrated, low drop-out linear voltage regulator in 180 nm cmos,”

Analog Integrated Circuits and Signal Processing, pp. 1–10, 2017.

C.-M. Chen, T.-W. Tsai, and C.-C. Hung, “Fast transient low-dropout

voltage regulator with hybrid dynamic biasing technique for soc ap-

plication,” IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, vol. 21, no. 9, pp. 1742–1747, 2013.

J. Esteves, J. Pereira, J. Paisana, and M. Santos, “Ultra low power capless ldo with dynamic biasing of derivative feedback,” Microelectronics

Journal, vol. 44, no. 2, pp. 94–102, 2013.

Y.-i. Kim and S.-s. Lee, “A capacitorless ldo regulator with fast feedback technique and low-quiescent current error amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 6, pp. 326–330,

C. Li and P. K. Chan, “Fvf ldo regulator with dual dynamic-load com-

posite gain stage,” Analog Integrated Circuits and Signal Processing,

pp. 1–10, 2017.

S. J. Yun, J. S. Kim, and Y. S. Kim, “Capless ldo regulator achieving-76

db psr and 96.3 fs fom,” IEEE Transactions on Circuits and Systems II:

Express Briefs, 2016.

X. Han, T. Burger, and Q. Huang, “An output-capacitor-free adaptively

biased ldo regulator with robust frequency compensation in 0.13 μm

cmos for soc application,” in Circuits and Systems (ISCAS), 2016 IEEE

International Symposium on. IEEE, 2016, pp. 2699–2702.

K. N. Leung and P. K. Mok, “A capacitor-free cmos low-dropout

regulator with damping-factor-control frequency compensation,” IEEE

Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691–1702, 2003.

S. K. Lau, P. K. Mok, and K. N. Leung, “A low-dropout regulator for

soc with q-reduction,” IEEE Journal of Solid-State Circuits, vol. 42,

no. 3, pp. 658–664, 2007.

X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, “A ldo regulator

with weighted current feedback technique for 0.47 nf–10 nf capacitive

load,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2658–

, 2014.

H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi,

and K. Sakui, “A cmos bandgap reference circuit with sub-1-v opera-

tion,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 670–674,

S. Hongprasit, W. Sa-Ngiamvibool, and A. Aurasopon, “Design of

bandgap core and startup circuits for all cmos bandgap voltage ref-

erence,” PRZEGLAD ELEKTROTECHNICZNY, vol. 88, no. 4 A, pp.

–280, 2012.

C. J. B. Fayomi, G. I. Wirth, H. F. Achigui, and A. Matsuzawa, “Sub 1 v

cmos bandgap reference design techniques: a survey,” Analog Integrated

Circuits and Signal Processing, vol. 62, no. 2, pp. 141–157, 2010.

P. Pérez-Nicoli, F. Veirano, P. C. Lisboa, and F. Silveira, “Low-power op-

erational transconductance amplifier with slew-rate enhancement based

on non-linear current mirror,” Analog Integrated Circuits and Signal

Processing, vol. 89, no. 3, pp. 521–529, 2016.


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