Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction

Michał Kruszewski, Wojciech Marek Zabołotny


This paper presents the design of a compact pro-
tocol for fixed-latency, high-speed, reliable, serial transmission
between simple field-programmable gate arrays (FPGA) devices.
Implementation of the project aims to delineate word boundaries,
provide randomness to the electromagnetic interference (EMI)
generated by the electrical transitions, allow for clock recov-
ery and maintain direct current (DC) balance. An orthogonal
concatenated coding scheme is used for correcting transmission
errors using modified Bose–Chaudhuri–Hocquenghem (BCH)
code capable of correcting all single bit errors and most of
the double-adjacent errors. As a result all burst errors of a
length up to 31 bits, and some of the longer group errors,
are corrected within 256 bits long packet. The efficiency of the
proposed solution equals 46.48%, as 119 out of 256 bits are
fully available to the user. The design has been implemented
and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit
with a data rate of 28.2 Gbps. Sample latency analysis has also
been performed so that user could easily carry out calculations
for different transmission speed. The main advancement of the
work is the use of modified BCH(15, 11) code that leads to high
error correction capabilities for burst errors and user friendly
packet length.

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J. Postel, “Transmission Control Protocol,” Tech. Rep., 1981. [Online].


G. Fairhurst and L. Wood, “Advice to link designers on link Automatic

Repeat reQuest (ARQ),” RFC Editor, Tech. Rep. RFC3366, Aug. 2002.

[Online]. Available:

C. Systems and C. Systems, “Interlaken Protocol Definition,” Tech. Rep.,

G. specifications group, “GBTX Manual,” Tech. Rep., Oct. 2016.

S. Mandal, J. Saini, W. M. Zabołotny, S. Sau, A. Chakrabarti, and

S. Chattopadhyay, “An FPGA-Based High-Speed Error Resilient Data

Aggregation and Control for High Energy Physics Experiment,” IEEE

Transactions on Nuclear Science, vol. 64, no. 3, pp. 933–944, Mar. 2017.

R. Giordano, V. Izzo, S. Perrella, and A. Aloisio, “A JESD204b-

Compliant Architecture for Remote and Deterministic-Latency Oper-

ation,” IEEE Transactions on Nuclear Science, vol. 64, no. 6, pp. 1225–

, Jun. 2017.

D. Gaisbauer, Y. Bai, S. Huber, I. Konorov, D. Levit, S. Paul, and

D. Steffen, “Unified Communication Framework,” IEEE Transactions

on Nuclear Science, vol. 64, no. 10, pp. 2761–2764, Oct. 2017.

E. Kadric, N. Manjikian, and Z. Zilic, “An FPGA implementation

for a high-speed optical link with a PCIe interface,” in 2012 IEEE

International SOC Conference, Sep. 2012, pp. 83–87.

B. Raahemi, “Error correction on 64/66 bit encoded links,” in Canadian

Conference on Electrical and Computer Engineering, 2005., May 2005,

pp. 412–416.

A. Wu, X. Jin, X. Du, and S. Guo, “A flexible FPGA-to-FPGA commu-

nication system,” in 2017 19th International Conference on Advanced

Communication Technology (ICACT), Feb. 2017, pp. 836–843.

J. Zhang, Q. Lin, Y. Zhang, and Z. Chen, “Design and Implementation of

High-Speed Data Transmission Scheme Between FPGA Boards Based

on Virtex -7 Series,” in 2018 2nd IEEE Advanced Information Man-

agement,Communicates,Electronic and Automation Control Conference

(IMCEC), May 2018, pp. 444–448.

R. Sanchez Correa and J. P. David, “Ultra-low latency communication

channels for FPGA-based HPC cluster,” Integration, vol. 63, pp. 41–55,

Sep. 2018. [Online]. Available:


Xilinx, “Source-Synchronous Serialization and Deserialization (up to

Mb/s),” Tech. Rep., 2013.

——, “LVDS Source Synchronous 7:1 Serialization and Deserialization

Using Clock Multiplication,” Tech. Rep., 2018.

I. Corporation, “Intel R Stratix R 10 High-Speed LVDS I/O User

Guide,” Tech. Rep., 2019.

Xilinx, “Native High-Speed I/O Interfaces,” Tech. Rep., 2017. [Online].



P. Samudrala, J. Ramos, and S. Katkoori, “Selective triple Modular

redundancy (STMR) based single-event upset (SEU) tolerant synthesis

for FPGAs,” IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp.

–2969, Oct. 2004.

K. S. Morgan, D. L. McMurtrey, B. H. Pratt, and M. J. Wirthlin, “A

Comparison of TMR With Alternative Fault-Tolerant Design Techniques

for FPGAs,” IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp.

–2072, Dec. 2007.

W. M. Zabolotny, I. M. Kudla, K. T. Pozniak, K. Bunkowski,

K. Kierzkowski, G. Wrochna, and J. Krolikowski, “Radiation tolerant

design of RLBCS system for RPC detector in LHC experiment,”

in Photonics Applications in Industry and Research IV, vol. 5948.

International Society for Optics and Photonics, Oct. 2005, p. 59481E.

[Online]. Available:



I. APT Technologies, D. C. Corporation, I. Corporation, I. Corporation,

M. Corporation, and S. Technology, “Serial ATA: High Speed Serialized

AT Attachment,” Aug. 2001.

S. Minami, J. Hoffmann, N. Kurz, and W. Ott, “Design and

implementation of a data transfer protocol via optical fiber - IEEE

Conference Publication.” [Online]. Available:


S. Cha and H. Yoon, “Single-Error-Correction and Double-Adjacent-

Error-Correction Code for Simultaneous Testing of Data Bit and Check

Bit Arrays in Memories,” IEEE Transactions on Device and Materials

Reliability, vol. 14, no. 1, pp. 529–535, Mar. 2014.

P. Reviriego, J. Martı́nez, S. Pontarelli, and J. A. Maestro, “A Method

to Design SEC-DED-DAEC Codes With Optimized Decoding,” IEEE

Transactions on Device and Materials Reliability, vol. 14, no. 3, pp.

–889, Sep. 2014.

C. Badack, T. Kern, and M. Gössel, “Modified DEC BCH codes for

parallel correction of 3-bit errors comprising a pair of adjacent errors,”

in 2014 IEEE 20th International On-Line Testing Symposium (IOLTS),

Jul. 2014, pp. 116–121.

X. She, N. Li, and D. W. Jensen, “SEU Tolerant Memory Using Error

Correction Code,” IEEE Transactions on Nuclear Science, vol. 59, no. 1,

pp. 205–210, Feb. 2012.

P. Reviriego, S. Pontarelli, A. Evans, and J. A. Maestro, “A Class

of SEC-DED-DAEC Codes Derived From Orthogonal Latin Square

Codes,” IEEE Transactions on Very Large Scale Integration (VLSI)

Systems, vol. 23, no. 5, pp. 968–972, May 2015.

N. Abramson, “A class of systematic codes for non-independent errors,”

IRE Transactions on Information Theory, vol. 5, no. 4, pp. 150–157,

Dec. 1959.

K.-M. Cheung and L. Swanson, “A performance comparison between

block interleaved and helically interleaved concatenated coding

systems,” Aug. 1989. [Online]. Available:


S. Cypress, “AN1047 - Understanding Bit-Error-Rate with HOTLink R ,”

Aug. 2017. [Online]. Available:


E. S. Chang and R. Taborek, “Recommendation of 10 ˆ-13 Bit Error

Rate for 10 Gigabit Ethernet,” Tech. Rep., Jul. 1999.

R. Dahlgren and B. Dahlgren, “NOISE IN FIBER OPTIC COMMUNI-


Xilinx, “UltraScale Architecture GTY Transceivers User Guide

(UG578),” Tech. Rep., 2017.

——, “AR# 69011: UltraScale+ GTY Transceiver: TX and RX Latency

Values.” [Online]. Available:



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