Designing Method of Compact n-to-2n Decoders

Ireneusz Brzozowski, Łukasz Zachara, Andrzej Kos


What decoder is, everyone knows. The paper presents fast and efficient method of layouts design of n-to- 2n-lines decoders. Two scenarios of layout arrangement are proposed and described. Based on a few building blocks only, especially prepared, and appropriate procedure of their placement, a decoder of any size can be build. Layouts of all needed fundamental blocks were designed in CMOS technology, as standard library. Moreover, some important parameters, such area, power dissipation and delay, were assessed and compared for decoders designed with proposed method and traditional. Power consumption were considered under extended model, which takes into account changes of input vectors, not only switching activity factor. All designs were done in UMC 180 CMOS technology.

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