2024-03-29T13:58:25Z
http://ijet.pl/index.php/ijet/oai
oai:ojs.ijet.ise.pw.edu.pl:article/2898
2021-08-31T09:43:27Z
ijet:ANALOG
"210830 2021 eng "
2300-1933
dc
A 5.5 μW 42nV/√Hz Chopper stabilized Amplifier for Biomedical Application with Input Impedance Enhancement
Adesara, Ankit Mukeshbhai
Nirma University
Indian Institute of Information Technology, Surat http://orcid.org/0000-0003-4458-0038
Naik, Amisha
Nirma University
VLSI; analog electronics; Biomedical application
The continuous real-time monitoring of diverse physical parameters using biosignals like ECG and EEG requires the biomedical sensors. Such sensor consists of analog frontend unit for which low noise and low power Operational transconductance amplifier (OTA) is essential. In this paper, the novel chopper-stabilized bio-potential amplifier is proposed. The chopper stabilization technique is used to reduce the offset and flicker noise. Further, the OTA is likewise comprised of a method to enhance the input impedance without consuming more power. Also, the ripple reduction technique is used at the output branch of the OTA. The designed amplifier consumes 5.5 μW power with the mid-band gain of 40dB. The pass-band for the designed amplifier is 0.1Hz to 1KHz. The input impedance is likewise boosted with the proposed method. The noise is 42 nV/√Hz with CMRR of 82 dB. All simulations are carried out in 180nm parameters.
Electronics and Telecommunications Committee
2021-08-30 02:53:27
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137842
International Journal of Electronics and Telecommunications; Vol 67, No 3 (2021)
eng
http://ijet.pl/index.php/ijet/article/download/2898/8368
http://ijet.pl/index.php/ijet/article/download/2898/9833
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/191
2015-03-31T11:08:29Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
New Structure of Test Pattern Generator Stimulating Crosstalks in Bus-type Connections
Garbolino, Tomasz
Silesian University of Technology
integrated circuit interconnections; crosstalk; test pattern generator; built in self-test; system-on-a chip
The paper discloses the idea of a new structure for a Test Pattern Generator (TPG) for detection of crosstalk faults that may happen to bus-type interconnections between built-in blocks within a System on a Chip structure. The new idea is an improvement of the TPG design proposed by the author in one of previous studies. The TPG circuit is meant to generate test sequences that guarantee detection of all crosstalk faults with the capacitance nature that may occur between individual lines within an interconnecting bus. The study comprises a synthesizable and parameterized model developed for the presented TPG in the VLSI Hardware Description Language (VHDL) with further investigation of properties and features of the offered module. The significant advantages of the proposed TPG structure include less area occupied on a chip and higher operation frequency as compared to other solutions. In addition, the design demonstrates good scalability in terms of both the hardware overhead and the length of the generated test sequence.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0009
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/1165
2018-07-20T19:13:02Z
ijet:ANALOG
"180720 2018 eng "
2300-1933
dc
CMOS ECCCII with Linear Tune of Rx and Its Application to Current-mode Multiplier
Sakul, Chaiwat
Rajamangala University of Technology Srivijaya, Trang Campus, 179 M.3 Mai Fad Sub-district, Sikao District, Trang 92150, Thailand.
Analog circuit design
In this paper present CMOS second-generation current-controlled-current-conveyor based on differential pair operational transconductance amplifier. Its parasitic resistance at x-port can be linearly controlled by an input bias current. Therefore, a proposed building block is called electronically tunable second-generation current-controlled-current-conveyor (ECCCII). The application presents 2-quadrant and 4-quadrant current-mode signal multiplier circuits. Characteristics of the proposed ECCCII and its application are simulated by the PSPICE program and they are in agreement with the theory.
Electronics and Telecommunications Committee
2018-07-20 21:02:23
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-123537
International Journal of Electronics and Telecommunications; Vol 64, No 3 (2018)
eng
http://ijet.pl/index.php/ijet/article/download/1165/3580
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/185
2015-03-31T18:49:11Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
Identification of Circuit Parameters for the Specified or Measured Performances
Rutkowski, Jerzy
Silesian University of Technology, Poland
analog circuits; parameter identification; fault diagnosis
The original method of analog circuit parameter identification for the specified design performances is described. These parameters are designated by means of PSpice simulation of the adjoint circuit to the original one. In this adjoint circuit, elements of the original circuit, described by the sized parameters, are replaced by controlled sources. Each such source is controlled by the differential voltage or current, difference between the calculated voltage or current and the specified one, with infinitely large gain. The method is applicable to both linear and nonlinear DC circuits and AC circuits and can be used in many fields of analog circuit design, such as: finding of acceptability region, analog fault diagnosis, postproduction identification and tuning. In the later cases, design performances are replaced by measurements of Circuit Under Test (CUT). Simplicity, extremely low computational complexity and high accuracy are the main benefits of the proposed, basic Circuit Theory based, approach – the solution is found after a single PSpice simulation. For better understanding of the presented methodology, four practical examples are discussed.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0012
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/3412
2021-12-19T22:25:19Z
ijet:ANALOG
"211201 2021 eng "
2300-1933
dc
Logarithmic ADC with accumulation of charge and impulse feedback – construction, principle of operation and dynamic properties
Mychuda, Zynovij
Lviv Polytechnic National University
Mychuda, Lesya
Lviv Polytechnic National University
Antoniv, Uliana
Lviv Polytechnic National University
Szcześniak, Adam
Kielce University of Technology http://orcid.org/0000-0003-2411-9279
Analog-to-digital converter, analysis, construction, charge accumulation, logarithm, modeling, impulse feedback
This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. LADC construction, principle of operation and dynamic properties were presented. They can also be part of more complex converters and systems based on LADC. LADC of this class is perspective for implementation in the form of integrated circuit, as the number of switched capacitors needed to conversion is minimized to one capacitor.
Electronics and Telecommunications Committee
2021-12-01 00:12:40
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137865
International Journal of Electronics and Telecommunications; Vol 67, No 4 (2021)
eng
http://ijet.pl/index.php/ijet/article/download/3412/10004
http://ijet.pl/index.php/ijet/article/download/3412/10308
http://ijet.pl/index.php/ijet/article/download/3412/10309
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/503
2016-06-20T10:16:45Z
ijet:ANALOG
"160620 2016 eng "
2300-1933
dc
Design of a Class-D Audio Amplifier With Analog Volume Control for Mobile Applications
El Khadiri, Karim
Faculté des sciences Dhar El Mehraz http://www.fsdmfes.ac.ma/
Qidaa, Hassan
Faculté des sciences Dhar El Mehraz http://www.fsdmfes.ac.ma/
A class-D audio amplifier with analog volume control (AVC) section and driver section for wireless and portable applications is proposed in this paper. The analog volume control section, including an integrator, an analog MUX, and a programmable gain amplifier (PGA) is implemented with three analog inputs (Audio, Voice, FM). For driver section, including a ramp generator, a comparator, a level shifter and a gate driver is designed to obtain a low distortion and a high
efficiency. Designed with 0.18 um 1P6M CMOS technology, the class-D audio amplifier with analog volume control achieves a total root-mean-square (RMS) output power of 0.5W, a total harmonic distortion plus noise (THD+N) at the 8-Ω load less than 0.06%, and a power efficiency of 89.9% with a total area of 1.74
mm2.
Electronics and Telecommunications Committee
2016-06-20 12:08:00
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0026
International Journal of Electronics and Telecommunications; Vol 62, No 2 (2016)
eng
http://ijet.pl/index.php/ijet/article/download/503/1643
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1196
2019-05-19T20:23:16Z
ijet:ANALOG
"190519 2019 eng "
2300-1933
dc
On and Off Chip Capacitor Free, Fast Response, Low Drop-out Voltage Regulator
Prasad, Guru
Manipal Academy of Higher Education, Deemed to be University http://orcid.org/0000-0001-6335-4429
Shama, Kumara
Manipal Academy of Higher Education, Deemed to be University
Analog Circuits;Voltage regulator
A low drop-out [LDO] voltage regulator with fast
transient response which does not require capacitor for proper
operation is proposed in this paper. Recent cap-less LDOs do
not use off chip capacitor but instead they use on chip capacitor
which occupy large area on chip. In the proposed LDO this on
chip capacitor is also avoided. A novel secondary local feed-back
technique is introduced which helps to achieve a good transient
response even in the absence of output capacitor. Further a
self compensating error amplifier is selected to eliminate the
need of compensating capacitor. Stability analysis shows that the
proposed LDO is stable with a phase margin of 78 0 . The proposed
LDO is laid out using Cadence spectre in 180 nm standard CMOS
technology. Post layout simulation is carried out and LDO gives
6mV/V and 360μV /mA line and load regulation respectively. An
undershoot of 120 mV is observed during the load transition
from 0 mA to 50 mA with 1 μs transition time, however LDO is
able to recover within 1.4μs. Since capacitor is not required in
any part of design, it occupies only 0.010824 mmXmm area on chip.
Electronics and Telecommunications Committee
2019-05-19 22:13:36
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.126296
International Journal of Electronics and Telecommunications; Vol 65, No 2 (2019)
eng
http://ijet.pl/index.php/ijet/article/download/1196/3666
http://ijet.pl/index.php/ijet/article/download/1196/3667
http://ijet.pl/index.php/ijet/article/download/1196/3668
http://ijet.pl/index.php/ijet/article/download/1196/3669
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/187
2015-03-31T18:48:23Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
Test Procedures for Synchronized Oscillators Network CMOS VLSI Chip
Kowalski, Jacek
Institute of Electronics
Lodz University of Technology
Strzelecki, Michał
Institute of Electronics
Lodz University of Technology
neural networks chip testing; synchronized oscillator s network; parallel image segmentation; analog - digital VLSI CMOS implementation
The paper presents test procedures designed for application-specific integrated circuit (ASIC) CMOS VLSI chip that implements a synchronized oscillator neural network with a matrix size of 32×32 for object detecting in binary images. Networks of synchronized oscillators are recently developed tool for image segmentation and analysis. This paper briefly introduces synchronized oscillators network. Basic chip analog building blocks with their test procedures and measurements results are presented. In order to do measurements, special basic building blocks test structures have been implemented in the chip. It let compare Spectre simulations results to measurements results. Moreover, basic chip analog building blocks measurements give precious information about their imperfections caused by MOS transistor mismatch. This information is very usable during design and improvement of a special setup for chip functional tests. Improvement of the setup is a digitally assisted analog technique. It is an idea of oscillators tuning procedure. Such setup, oscillators tuning procedure and segmentation of a sample binary image are presented.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0013
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
http://ijet.pl/index.php/ijet/article/download/187/575
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/3413
2021-12-19T22:25:58Z
ijet:ANALOG
"211201 2021 eng "
2300-1933
dc
Logarithmic ADC with accumulation of charge and impulse feedback – analysis and modeling
Mychuda, Zynoviy
Lviv Polytechnic National University
Mychuda, Lesya
Lviv Polytechnic National University
Antoniv, Uliana
Lviv Polytechnic National University
Szcześniak, Adam
University of Technology In Kielce http://orcid.org/0000-0003-2411-9279
Analog-to-digital converter; analysis; construction; charge accumulation; logarithm; modeling; impulse feedback
This article is a presentation of the analysis of new class of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback. Development of mathematical models of errors, quantitative assessment of these errors taking into account modern components and assessing the accuracy of logarithmic analog-to-digital converter (LADC) with accumulation of charge and impulse feedback were presented.
Electronics and Telecommunications Committee
2021-12-01 00:12:40
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137866
International Journal of Electronics and Telecommunications; Vol 67, No 4 (2021)
eng
http://ijet.pl/index.php/ijet/article/download/3413/10007
http://ijet.pl/index.php/ijet/article/download/3413/10310
http://ijet.pl/index.php/ijet/article/download/3413/10311
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/637
2018-04-29T19:24:17Z
ijet:ANALOG
"170418 2017 eng "
2300-1933
dc
A New Grounded Current Controlled Inductor Based on Simplified Current Conveyors
M'harzi, Zineb
INPT-Rabat
ALAMI, Mustapha
INPT-Rabat
TEMCAMANI, Farid
ENSEA, France
Active inductor; bandpass filter; BiCMOS technology; Integrated Circuit (IC); Second Generation Current Controlled Conveyor (CCCII).
In this paper, a new active grounded inductor controlled in current is described. This structure is realized using negative second generation current controlled conveyors and a single grounded capacitor, with no external resistance. The proposed circuit offers many advantages, such as: operation at high frequencies, simple circuit, tuning by the bias current, low power dissipation, etc. Comparison between this topology and those presented in literature is done to highlight the benefits of our structure. As an application, a bandpass filter based on the proposed active inductance is constructed to confirm the usability of the circuit and illustrate these performances. The filter center frequency and quality factor can be tuned independently. Simulation results, given under PSPICE software, present good agreement with the theoretical ones.
Electronics and Telecommunications Committee
2017-04-18 16:24:06
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0030
International Journal of Electronics and Telecommunications; Vol 63, No 2 (2017)
eng
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1952
2019-05-19T20:23:16Z
ijet:ANALOG
"190519 2019 eng "
2300-1933
dc
Compact thermal models of semiconductor devices – a review
Górecki, Krzysztof
Uniwersytet Morski w Gdyni
Zarębski, Janusz
Uniwersytet Morski w Gdyni
Górecki, Paweł
Uniwersytet Morski w Gdyni
Ptak, Przemysław
Uniwersytet Morski w Gdyni
electronics
In the paper the problem of modelling thermal properties of semiconductor devices with the use of compact models is presented. This class of models is defined and their development over the past dozens of years is described. Possibilities of modelling thermal phenomena both in discrete semiconductor devices, monolithic integrated circuits, power modules and selected electronic circuits are presented. The problem of the usefulness range of compact thermal models in the analysis of electronic elements and circuits is discussed on the basis of investigations performed in Gdynia Maritime University.
Electronics and Telecommunications Committee
2019-05-19 22:13:36
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.126295
International Journal of Electronics and Telecommunications; Vol 65, No 2 (2019)
eng
http://ijet.pl/index.php/ijet/article/download/1952/5675
http://ijet.pl/index.php/ijet/article/download/1952/5677
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/190
2015-03-31T11:08:29Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
The On-line Evolutionary Method for Soft Fault Diagnosis in Diode-transistor Circuits
Korzybski, Marek
Lodz University of Technology
Ossowski, Marek
Lodz University of Technology
electronic circuits testing; fault diagnosis; evolutionary methods
The paper is devoted to diagnostic method enabling us to perform all the three levels of fault investigations, it means, detection, localization and identification. It is designed for analog diode-transistor circuits, in which the circuit state is defined by DC sources values causing elements operating points and the harmonic components with small amplitudes being calculated in accordance with small signal circuit analysis rules. Gene expression programming (GEP), differential evolution (DE) and genetic algorithms (GA) are a mathematical background of the proposed algorithms. Time consumed by diagnostic process rises rapidly with the increasing number of possible faulty circuit elements in case of using any of mentioned algorithms. Use of two different circuit models with partly different elements allows us to decrease a number of possibly faulty and possibly concurrently faulty elements in all of them, and results in an increasing number of measurement points. This significantly increases probability of creating conditions for carrying out an effective on-line circuit testing, without necessity of performing additional simulations.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0014
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
http://ijet.pl/index.php/ijet/article/download/190/856
http://ijet.pl/index.php/ijet/article/download/190/857
http://ijet.pl/index.php/ijet/article/download/190/858
http://ijet.pl/index.php/ijet/article/download/190/859
http://ijet.pl/index.php/ijet/article/download/190/860
http://ijet.pl/index.php/ijet/article/download/190/861
http://ijet.pl/index.php/ijet/article/download/190/862
http://ijet.pl/index.php/ijet/article/download/190/863
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/3241
2021-12-19T22:27:13Z
ijet:ANALOG
"211201 2021 eng "
2300-1933
dc
Study of a high-voltage switching power supply pa-rameters
Martemianov, Boris
VTC BASPIK, Ltd.
Ryzhkov, Alexander
VTC BASPIK, Ltd.
Vdovin, Grigoriy
VTC BASPIK, Ltd.
A principle diagram of a high-voltage low-power power supply for devices comprising a microchannel plate (MCP) has been developed. A mathematical model was built according to the developed scheme for a detailed study of the operation of the power supply and the selection of the optimal parameters of its components and obtaining the best output voltages. The power supply circuit comprises a control circuit, a pulse transformer, a voltage multiplier circuit, a feedback circuit, and an input stabilizer. The input stabilizer provides the maintenance of the voltage switched in the primary winding of the transformer at a given level regardless of the voltage drop of the power supply primary source. Moreover the stabilizer provides constant voltage maintenance when the load resistance changes. (with Rload changing from 100 to 200 MΩ, Uout did not exceed 3 V)
Electronics and Telecommunications Committee
2021-12-01 00:12:40
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137867
International Journal of Electronics and Telecommunications; Vol 67, No 4 (2021)
eng
http://ijet.pl/index.php/ijet/article/download/3241/9507
http://ijet.pl/index.php/ijet/article/download/3241/10512
http://ijet.pl/index.php/ijet/article/download/3241/10513
http://ijet.pl/index.php/ijet/article/download/3241/10514
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/781
2018-02-01T12:59:01Z
ijet:ANALOG
"180131 2018 eng "
2300-1933
dc
Sinusoidal Oscillator Circuits Reexamined
Prasad, VIshnuvajjula Charan
Dayalbagh Educational Institute
Analog electroncis; Sinusoidal oscillators
Singular network condition is proposed to study oscillators. It states that a circuit is a potential oscillator if and only if the rank of the network matrix of size n X n is (n -1) at the frequency of oscillations . The dual (if it exists) and adjoint circuits of an oscillator are also oscillators. Limitations of Barkhausen’s approach are pointed out . It is explained that there are many ways to generate oscillations other than Barkhausen’s positive feedback configuration. The new approach emphasises that appropriate D C inputs / initial conditions are important.
Electronics and Telecommunications Committee
2018-01-31 23:49:35
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-118152
International Journal of Electronics and Telecommunications; Vol 64, No 1 (2018)
eng
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/183
2015-03-31T11:08:29Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
New Aspects of Fault Diagnosis of Nonlinear Analog Circuits
Tadeusiewicz, Michał
Lodz University of Technology
Hałgas, Stanisław
Kuczyński, Andrzej
Lodz University of Technology
Analog circuits; fault diagnosis; local and global diagnosis; multiple soft faults; nonlinear circuits; single hard faults
The paper is focused on nonlinear analog circuits, with the special attention paid to circuits comprising bipolar and MOS transistors manufactured in micrometer and submicrometer technology. The problem of fault diagnosis of this class of circuits is discussed, including locating faulty elements and evaluating their parameters. The paper deals with multiple parametric fault diagnosis using the simulation after test approach as well as detection and location of single catastrophic faults, using the simulation before test approach. The discussed methods are based on diagnostic test, leading to a system of nonlinear algebraic type equations, which are not given in explicit analytical form. An important and new aspect of the fault diagnosis is finding multiple solutions of the test equation, i.e. several sets of the parameters values that meet the test. Another new problems in this area are global fault diagnosis of technological parameters in CMOS circuits fabricated in submicrometer technology and testing the circuits having multiple DC operating points. To solve these problems several methods have been recently developed, which employ different concepts and mathematical tools of nonlinear analysis. In this paper they are sketched and illustrated. All the discussed methods are based on the homotopy (continuation) idea. It is shown that various versions of homotopy and combinations of the homotopy with some other mathematical algorithms lead to very powerful tools for fault diagnosis of nonlinear analog circuits. To trace the homotopy path which allows finding multiple solutions, the simplicial method, the restart method, the theory of linear complementarity problem and Lemke's algorithm are employed. For illustration four numerical examples are given.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0011
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/2487
2020-09-10T21:07:52Z
ijet:ANALOG
"200907 2020 eng "
2300-1933
dc
Application of the averaged model of the diode-transistor switch for modelling characteristics of a boost converter with an IGBT
Górecki, Paweł
Gdynia Maritime University http://orcid.org/0000-0001-5544-2373
Electronics, analog circuits, modelling
DC-DC converters are popular switch-mode electronic circuits used in power supply systems of many electronic devices. Designing such converters requires reliable computation methods and models of components contained in these converters, allowing for accurate and fast computations of their characteristics. In the paper, a new averaged model of a diode-transistor switch containing an IGBTis proposed. The form of the developed model is presented. Its accuracy is verified by comparing the computed characteristics of the boost converter with the characteristics computed in SPICE using a transient analysis and literature models of a diode and an IGBT. The obtained results of computations proved the usefulness of the proposed model.
Electronics and Telecommunications Committee
2020-09-07 19:51:59
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134012
International Journal of Electronics and Telecommunications; Vol 66, No 3 (2020)
eng
http://ijet.pl/index.php/ijet/article/download/2487/7432
http://ijet.pl/index.php/ijet/article/download/2487/7434
http://ijet.pl/index.php/ijet/article/download/2487/7480
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/189
2015-03-31T11:08:29Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
Construction of an Expert System Based on Fuzzy Logic for Diagnosis of Analog Electronic Circuits
Grzechca, Damian
Silesian University of Technology
analogue circuits; fault diagnosis; system testing; fuzzy expert system; sensitivity analysis
The paper presents construction of the fuzzy logic system to analog circuits soft fault diagnosis. The classical dictionary construction is replaced by fuzzy rule system. The first part refers to analog fault diagnosis, its techniques, approaches and goals. It clarifies common strategy and define differences between detecting, locating and identifying a fault in analog electronic circuit. The second part is focused on a creation of fuzzy rule expert system with use of sensitivity functions and known circuit topology. To detect, locate and identify a faulty element in a circuit the sensitivity matrix is used. The advantage of the method is its utilization in all, AC, DC and time domain. The fuzzy system, like the classical fault dictionary, can detect and locate single catastrophic faults and, on the contrary to the classical one, it also detects and locates parametric faults. Moreover, it allows identification of these faults, such that sign of the faulty parameter deviation is designated. The method has deterministic character as well as it can be applied on the verification and production stage.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0010
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
Copyright (c)
oai:ojs.ijet.ise.pw.edu.pl:article/3786
2023-02-27T00:37:28Z
ijet:ANALOG
"230227 2023 eng "
2300-1933
dc
Passive Mixer-based UWB Receiver with Low Loss, High Linearity and Noise-cancelling for Medical Applications
Kareem, Thaar Abdalraheem
Systems Integration & Emerging Energies Laboratory, Electrical Engineering Department, National Engineers School of Sfax, University of Sfax, Sfax, Tunisia
Trabelsi, Hatem
Systems Integration & Emerging Energies Laboratory, Electrical Engineering Department, National Engineers School of Sfax, University of Sfax, Sfax, Tunisia
A double balanced passive mixer-based receiver operating in the 3-5 GHz UWB for medical applications is described in this paper. The receiver front-end circuit is composed of an inductorless low noise amplifier (LNA) followed by a fully differential voltage-driven double-balanced passive mixer. A duty cycle of 25% was chosen to eliminate overlap between LO signals, thereby improving receiver linearity. The LNA realizes a gain of 25.3 dB and a noise figure of 2.9 dB. The proposed receiver achieves an IIP3 of 3.14 dBm, an IIP2 of 17.5 dBm and an input return loss (S11) below -12.5dB. Designed in 0.18μm CMOS technology, the proposed mixer consumes 0.72pW from a 1.8V power supply. The designed receiver demonstrated a good ports isolation performance with LO_IF isolation of 60dB and RF_IF isolation of 78dB.
Electronics and Telecommunications Committee
2023-02-27 01:32:20
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.144332
International Journal of Electronics and Telecommunications; Vol 69, No 1 (2023)
eng
http://ijet.pl/index.php/ijet/article/download/3786/11615
http://ijet.pl/index.php/ijet/article/download/3786/11630
Copyright (c) 2023 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1132
2018-02-01T12:59:01Z
ijet:ANALOG
"180131 2018 eng "
2300-1933
dc
Influence of thermal phenomena on dc characteristics of the IGBT
Górecki, Krzysztof
Gdynia Maritime University
Górecki, Paweł
Gdynia Maritime University
electronics; power semiconductor devices
The paper concerns the study of the effect of thermal phenomena on characteristics of the IGBT. The used measurement set-ups and the results of measurements of dc characteristics of the selected transistor obtained under different cooling conditions are presented. The influence of the ambient temperature and the applied cooling system on the shape of these characteristics is discussed. In particular, attention has been paid to the untypical shape of non-isothermal characteristics of this element in the sub-threshold range.
Electronics and Telecommunications Committee
2018-01-31 23:49:35
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-118149
International Journal of Electronics and Telecommunications; Vol 64, No 1 (2018)
eng
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/186
2015-03-31T18:46:49Z
ijet:ANALOG
"150316 2015 eng "
2300-1933
dc
Automatic Test Bench for Selected Transmission Parameters of Power Line Conductors
Chruszczyk, Łukasz
Silesian University of Technology
LabVIEW; power line measurements; Power Line Communication; amplitude spectrum; phase spectrum; crosstalk measurement
This paper presents automatic test bench used for measurement of selected high frequency parameters of a power copper line. The aim is fast estimation of line behavior in context of Power Line Communication (PLC). The hardware interface uses sinusoidal waveform generator, digital oscilloscope and a PC-class computer. The software interface created in LabView environment performs signal processing and data presentation.
Electronics and Telecommunications Committee
2015-03-31 13:02:37
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0008
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015)
eng
http://ijet.pl/index.php/ijet/article/download/186/572
Copyright (c)