2024-03-29T10:49:51Z
http://ijet.pl/index.php/ijet/oai
oai:ojs.ijet.ise.pw.edu.pl:article/3380
2022-03-08T12:08:31Z
ijet:SIGNALS
Urukul – open-source frequency synthesizer module for quantum physics
Kasprowicz, Grzegorz
Harty, Thomas
Bourdeauducq, Sébastien
Jördens, Robert
Allcock, David
Nadlinger, David
Britton, Joseph
Sotirova, Ana
Nowicka, Dorota
We describe Urukul, a frequency synthesizer based on direct digital synthesis (DDS), optimized for wave generate control in atomic, molecular and optical (AMO) physics experiments. The Urukul module is a part of the Sinara family of modular, open-source hardware designed for the ARTIQ quantum operating system. The Urukul has 4-channel, sub-Hz frequency resolution, controlled phase steps and accurate output amplitude control. The module is available in two population variants. This paper presents Urukul module construction and obtained characteristics
Electronics and Telecommunications Committee
the Polish National Agency for Academic Exchange - NAWA
2022-02-26
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139859
International Journal of Electronics and Telecommunications; Vol 68, No 1 (2022); 123-128
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139859/937
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139859/2890
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139859/2891
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139859/2892
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139859/2893
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/626
2017-10-31T00:24:38Z
ijet:SIGNALS
Design and development of Detector Simulator for Total Ionized Dose and ground checkout system of radiation monitoring instrument
Bhatt, Chintan
Mahant, Keyur
This Paper describes the simulator development for the Total Ionizing Dose (TID) measurement of radiation monitoring instrument. The TID Detector (UDOS001-micro dosimeter) is a compact hybrid microcircuit which directly measures Total Ionizing Dose absorbed by an internal silicon test mass. The developed detector simulator, simulates the equivalent Total Ionized Dose absorbed from the space radiation and Ground checkout simulator receive the data from Radiation monitoring Instrument through UART and process it for the functional verification of the Radiation monitoring Instrument, which is discussed in the paper.
Electronics and Telecommunications Committee
CHARUSAT Space & Research Technology Center
2017-10-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0059
International Journal of Electronics and Telecommunications; Vol 63, No 4 (2017); 431-436
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0059/425
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/432
2016-09-08T11:39:19Z
ijet:SIGNALS
Analysis and design of colpitts oscillator for short-range WSN
yousefi, Mousa
In this paper, analysis and design of colpitts oscillator with ability to transmit data at low output power with application in short-range wireless sensor networks such as MICS is described. Reducing the area required to implement the transmitter, on-chip implementation and appropriate energy efficiency are the advantages of this structure that makes it suitable for the design of short-range transmitter in biomedical applications. The proposed OOK transmitter works at 400 MHz with 10 Mbps data rate. Output power and total power consumption are 25 µW and 670 µW, respectively. Energy efficiency is 67 pJ/bit. The transmitter has been designed and simulated in 0.18 µm CMOS technology.
Electronics and Telecommunications Committee
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0038
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 279-282
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0038/300
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3009
2021-01-31T00:11:06Z
ijet:SIGNALS
Approaches to evaluating the quality of masking noise interference
Smailov, Nurzhigit
Batyrgaliev, Askhat
Akhmediyarova, Ainur
Seilova, Nurgul
Koshkinbayeva, Madina
Baigulbayeva, Moldir
Romaniuk, Ryszard
Orunbekov, Maxat
Assem, Kabdoldina
Kotyra, Andrzej
The paper discusses the characteristics of spatial electromagnetic noise generators, as well as the formation of a broadband noise signal. A number of well-known methods for assessing the quality of masking noise interference and the approaches used in them have been described. Approaches to the measurement of masking noise were also determined in assessing their quality. In conclusion, additional methods are proposed for assessing the quality of masking noises, such as searching for correlation of noise in different frequency sub-bands and using statistical and (or) graphical methods (tests) for randomness.
Electronics and Telecommunications Committee
2021-01-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135944
International Journal of Electronics and Telecommunications; Vol 67, No 1 (2021); 59-64
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135944/778
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135944/2592
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135944/2593
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2352
2020-06-01T14:11:57Z
ijet:SIGNALS
Modernization of DVB-S2 Standard Using Signal-Code Constructions Based on Amplitude Modulation of Many Components
Horbatyi, Ivan Volodymyrovych
Yashchyshyn, Yevhen
DVB-S2 standard, frequency efficiency, energy efficiency, amplitude modulation of many components
It is proposed to modernize the DVB-S2 standard by using AMMC (amplitude modulation of many components) signals instead of 8PSK (8-phase shift keying) and APSK (amplitude-phase shift keying) signals, and to modernize the DVB-S2 standard equipment by using the AMMC modulator and AMMC demodulator. Usage of AMMC makes it possible to reduce the symbol error rate in communication channel up to 52 times. The satellite digital video broadcast systems that apply signal-code constructions based on AMMC are characterized by a higher energy efficiency from 1 to 2.6 dB compared with signal-code constructions based on 8PSK and APSK.
Electronics and Telecommunications Committee
This work was supported by Ministry of Education and Science of Ukraine under project No 0118U000261.
2020-06-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131880
International Journal of Electronics and Telecommunications; Vol 66, No 2 (2020); 315-320
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131880/698
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.131880/2211
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/104
2015-09-23T20:16:34Z
ijet:SIGNALS
Derivation of Closed-Form Design Equations for Idealized Operation of Inverse Class-E Power Amplifiers at Any Duty Ratio
Wang, Yelin
Foo, Suan-Kien
He, Qibing
Class-E; power amplifier; numerical simulation.
Complementary to the conventional class-E topology, inverse class-E operation has several advantages over the class-E counterpart, such as lower peak switch voltage and smaller circuit inductance, which are attractive to high power RF design and MMIC implementation. This paper derives the closed-form design equations that can be used to synthesize the idealized operation of inverse class-E power amplifiers at any switch duty ratio. Calculation of the key design parameters, such as the maximum switch voltage and circuit components values, is elaborated and compared with the case of conventional class-E operation. Further, the theoretical analysis is confirmed and verified by numerical simulations performed on a 500mW, 2.4GHz idealized inverse class-E power amplifier.
Electronics and Telecommunications Committee
2015-08-26
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0037
International Journal of Electronics and Telecommunications; Vol 61, No 3 (2015); 281-287
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0037/187
oai:ojs.ijet.ise.pw.edu.pl:article/4169
2023-07-31T01:06:51Z
ijet:SIGNALS
Development of methodological, hardware, and software of the incoherent scatter radar of Institute of Ionosphere (Kharkiv, Ukraine)
Emelyanov, Leonid
Miroshnikov, Artem
incoherent scatter radar; incoherent scatter signal; signal reception and processing; ionospheric plasma parameters
We present the methodological features and new subsystem for receiving, digitizing and processing signals at the intermediate frequency of the incoherent scatter (IS) radar. The implemented method, subsystem and flexible software made it possible to avoid the influence of a number of instrumental factors on the accuracy of determining the quadrature components of the IS signal correlation function used to determine the ionospheric parameters, to adapt the digital filtering parameters, the value of the correlation delay step and the number of ordinates of the measured correlation function to IS signals from different altitudes and under different space weather conditions, to effectively test radar systems for the subsequent taking into account hardware factors and, thus, to improve the accuracy of the measured ionospheric parameters. The experimental results are presented.
Electronics and Telecommunications Committee
2023-07-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.146510
International Journal of Electronics and Telecommunications; Vol 69, No 3 (2023); 579-586
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.146510/1132
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146510/4015
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146510/4017
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146510/4018
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146510/4019
Copyright (c) 2023 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1775
2019-09-06T13:37:12Z
ijet:SIGNALS
Low Power and Improved Speed Montgomery Multiplier using Universal Building Blocks
Pitchandi, Velrajkumar
Chinnayan, Senthilpari
Joseph, Sheela Francisca
Raj, Nirmal
VLSI, Electronic ciruits
This paper describes the arithmetic blocks based on Montgomery Multiplier (MM), which reduces complexity, gives lower power dissipation and higher operating frequency. The main objective in designing these arithmetic blocks is to use modified full adder structure and carry save adder structure that can be implemented in algorithm based MM circuit. The conventional full adder design acts as a benchmark for comparison, the second is the modified Boolean equation for full adder and third design is the design of full adder consisting of two XOR gate and a 2-to-1 Multiplexer. Besides Universal gates such as NOR gate and NAND gate, full adder circuits are used to further improve the speed of the circuit. The MM circuit is evaluated based on different parameters such as operating frequency, power dissipation and area of occupancy in FPGA board. The schematic designs of the arithmetic components along with the MM architecture are constructed using Quartus II tool, while the simulation is done using Model sim for verification of circuit functionality which has shown improvement on the full adder design with two XOR gate and one 2-to-1 Multiplexer implementation in terms of power dissipation, operating frequency and area.
Electronics and Telecommunications Committee
2019-09-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129802
International Journal of Electronics and Telecommunications; Vol 65, No 3 (2019); 477-483
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129802/610
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3277
2021-12-19T22:55:04Z
ijet:SIGNALS
High performance DIF-FFT using dissimilar partitioned LUT based Distributed Arithmetic
Jammu, Bhaskara Rao
Muntha, Charan
Cheepurupalli, Kusma Kumari
S, Noor Mahammad
Fast Fourier Transform, Adders, Distributed Arithmetic, DSP.
Real-time data processing systems utilize Digital Signal Processing (DSP) functions as the base modules. Most of the DSP functions involve the implementation of Fast Fourier Transform (FFT) to convert the signals from one domain to another domain. The major bottleneck of Decimation in frequency-Fast Fourier Transform (DIF-FFT) implementation lies in using a number of Multipliers. Distributed arithmetic (DA) is considered as one of the efficient techniques to implement DIF-FFT. In this approach, the multipliers are not used. The proposed technique exploits the very advantage of the look-up table by storing the Twiddle factors, thereby avoiding the multipliers required in the butterfly structure. DIF-FFT using Distributed Arithmetic (DIF-FFT DA) models, with different adders such as Ripple carry adder (RCA), Carry-lookahead adder (CLA), and Sklansky prefix graph adder, are proposed in this paper. The three proposed models are synthesized using Cadence 6.1 EDA tools with a 45nm CMOS technology. Compared to the traditional method, it is observed that the area is improved by 53.11%, 53.35%, and 50.15%, power is improved by 42.31%, 42.52%, and 40.39%, and delay is improved by 45.26%, 45.42%, 41.80%, respectively.
Electronics and Telecommunications Committee
2021-12-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137856
International Journal of Electronics and Telecommunications; Vol 67, No 4 (2021); 631-637
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137856/907
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137856/2772
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137856/3031
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137856/3032
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137856/3057
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/422
2018-04-29T19:24:17Z
ijet:SIGNALS
Mathematical Modelling and Analysis of Memristors with and without its Temperature Effects
Ammula, Haritha
Prasad, Bhavani
maddu, Kamaraju
Lakshmi, Venkata
In this paper the main goal is to study the principle structure and characteristics of single and multiple memristors and also the temperature effects. The complete analysis described here is done by using matlab Simulink. The relationship between the on resistance, off resistance and ionic mobility with respect to temperature has been analyzed and shown graphically. The memristor can be used as a High speed switch and it can be used in non volatile computer memories due to its higher switching speeds.
Electronics and Telecommunications Committee
2017-04-18
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0024
International Journal of Electronics and Telecommunications; Vol 63, No 2 (2017); 181-186
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0024/375
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/412
2016-02-17T16:08:38Z
ijet:SIGNALS
Relationships between two definitions of fading memory for discrete-time systems
Borys, Andrzej Marek
Nonlinear systems; fading memory
In this paper, we refer to two definitions of fading memory property, which were published in the literature, for discrete-time circuits and systems. One of these definitions relates to systems working with signals (sequences) defined for both the positive and negative integers, expanding from minus infinity to plus infinity. On the other hand, the second one refers to systems processing sequences defined only for nonnegative integers, that is starting at the discrete-time point equal to zero and expanding to plus infinity. We show here that the second definition follows from the first one. That is they are not independent. Moreover, we also show that if an operator describing a system possesses a fading memory according to the second definition, then its associated operator has this property, too, but in accordance with the first definition.
Electronics and Telecommunications Committee
2015-12-24
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0049
International Journal of Electronics and Telecommunications; Vol 61, No 4 (2015); 377-380
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0049/216
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0049/228
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0049/272
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0049/273
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0049/397
Copyright (c) 2015 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2959
2021-05-11T08:41:30Z
ijet:SIGNALS
An Enhanced IEEE1588 Clock Synchronization for Link Delays Based on a System-on-Chip Platform
Wei, Xiaohan
Xiong, Xingzhong
Luo, Zhongqiang
Wang, Jianwu
Cheng, Kaixing
(Embedded Systems)
The clock synchronization is considered as a key technology in the time-sensitive networking (TSN) of 5G fronthaul. This paper proposes a clock synchronization enhancement method to optimize the link delays, in order to improve synchronization accuracy. First, all the synchronization dates are filtered twice to get the good calculation results in the processor, and then FPGA adjust the timer on the slave side to complete clock synchronization. This method is implemented by Xilinx Zynq UltraScale+ MPSoC (multiprocessor system-on-chip), using FPGA+ARM software and hardware co-design platform. The master and slave output Pulse Per-Second (PPS) signals. The synchronization accuracy was evaluated by measuring the time offset between PPS signals. Contraposing the TSN, this paper compares the performance of the proposed scheme with some previous methods to show the efficacy of the proposed work. The results show that the slave clock of proposed method is synchronized with the master clock, leading to better robustness and significant improvement in accuracy, with time offset within the range of 40 nanoseconds. This method can be applied to the time synchronization of the 5G open fronthaul network and meets some special service needs in 5G communication.
Electronics and Telecommunications Committee
Sichuan Outstanding Youth Fund Project
2021-05-11
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135978
International Journal of Electronics and Telecommunications; Vol 67, No 2 (2021); 289-294
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135978/815
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135978/2427
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135978/2428
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2210
2020-11-22T18:22:53Z
ijet:SIGNALS
ZA-APA with Adaptive Zero Attractor Controller for Variable Sparsity Environment
Radhika, S.
Chandrasekar, A.
Nirmalraj, S.
School of electrical and electronics,Department of electrical and electronics engineering
The zero attraction affine projection algorithm (ZA-APA) achieves better performance in terms of convergence rate and steady state error than standard APA when the system is sparse. It uses l1 norm penalty to exploit sparsity of the channel. The performance of ZA-APA depends on the value of zero attractor controller. Moreover a fixed attractor controller is not suitable for varying sparsity environment. This paper proposes an optimal adaptive zero attractor controller based on Mean Square Deviation (MSD) error to work in variable sparsity environment. Experiments were conducted to prove the suitability of the proposed algorithm for identification of unknown variable sparse system.
Electronics and Telecommunications Committee
2020-11-22
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134029
International Journal of Electronics and Telecommunications; Vol 66, No 4 (2020); 695-700
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134029/751
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.134029/2320
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/44
2014-07-03T17:43:47Z
ijet:SIGNALS
A -5 dBm 400MHz OOK Transmitter for Wireless Medical Application
Yousefi, Mousa
A 400 MHz high efficiency transmitter forwireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies isproposed to achieve high data rate with low powerconsumption. In the on-off keying transmitters, the oscillatorand power amplifier are turned off when the transmittersends 0 data. The proposed class-e power amplifier has highefficiency for low level output power. The proposed on-offkeying transmitter consumes 1.52 mw at -5 dBm output by 40Mbps data rate and energy consumption 38 pJ/bit. Theproposed transmitter has been designed in 0.18µm CMOStechnology.
Electronics and Telecommunications Committee
2014-06-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0024
International Journal of Electronics and Telecommunications; Vol 60, No 2 (2014); 193-197
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0024/32
oai:ojs.ijet.ise.pw.edu.pl:article/3631
2022-05-31T02:27:45Z
ijet:SIGNALS
The Problem of Aliasing and Folding Effects in Spectrum of Sampled Signals in View of Information Theory
Borys, Andrzej Marek
systems; signals; signal processing; information theory
In this paper, the problem of aliasing and folding effects in spectrum of sampled signals in view of Information Theory is discussed. To this end, the information content of deterministic continuous time signals, which are continuous functions, is formulated first. Then, this notion is extended to the sampled versions of these signals. In connection with it, new signal objects that are partly functions but partly not are introduced. It is shown that they allow to interpret correctly what the Whittaker–Shannon reconstruction formula in fact does. With help of this tool, the spectrum of the sampled signal is correctly calculated. The result achieved demonstrates that no aliasing and folding effects occur in the latter. Finally, it is shown that a Banach–Tarski-like paradox can be observed on the occasion of signal sampling.
Electronics and Telecommunications Committee
2022-05-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139884
International Journal of Electronics and Telecommunications; Vol 68, No 2 (2022); 315--322
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139884/972
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139884/3227
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1120
2018-04-27T08:36:48Z
ijet:SIGNALS
Application of Neural Network for Testing selected specification parameters of Voltage-Controlled Oscillator
Temich, Sebastian
Grzechca, Damian
Specification driven testing, voltage-controlled oscillator, ring oscillator, artificial neural network
In this paper, the application of the Artificial Neural Network (ANN) algorithm has been used for testing selected specification parameters of voltage-controlled oscillator. Today, mixed electronic circuits specification time is an issue. An analog part of Phase Locked Loop is a voltage-controlled oscillator, which is very sensitive to variation of the technology process. Fault model for the integrated circuit voltage control oscillator (VCO) in ring topology is introduced and the before test stage classificatory is designed. In order to reduce testing time and keep the specification accuracy (approximation) on the high level, an artificial neural network has been applied. The features selection process and output coding for specification parameters are described. A number of different ANN have been designed and then compared with real specification of the VCO. The results obtained gives response in short time with high enough accuracy.
Electronics and Telecommunications Committee
This work was supported by the Ministry of Science and Higher Education funding for statutory activities
2018-04-27
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-119371
International Journal of Electronics and Telecommunications; Vol 64, No 2 (2018); 203-207
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-119371/459
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-119371/908
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-119371/910
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-119371/984
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-119371/985
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/633
2016-09-08T11:39:19Z
ijet:SIGNALS
On Modelling AM/AM and AM/PM Conversions via Volterra Series
Borys, Andrzej Marek
Sieńko, Wiesław
Telecommunications; RF communication systems
In this paper, we present the expressions, not published up to now, that describe the AM/AM and AM/PM conversions of communication power amplifiers (PAs) via the Volterra series based nonlinear transfer functions. Furthermore, we present a necessary and sufficient condition of occurrence of the nonzero values of AM/PM conversion in PAs. Moreover, it has been shown that Saleh’s approach and related ones, which foresee nonzero level of AM/PM conversion, are not models without memory. It has been also shown that using a polynomial description of a PA does not lead to a nonzero AM/PM conversion. Moreover, a necessary condition of occurrence of an AM/AM conversion in this kind of modelling is existence of at least one nonzero polynomial coefficient associated with its odd terms of degree greater than one.
Electronics and Telecommunications Committee
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0036
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 267-272
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0036/290
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3344
2021-08-31T09:43:27Z
ijet:SIGNALS
A method for soft fault diagnosis of linear analog circuit using the Laplace transform technique
Tadeusiewicz, Michał
Ossowski, Marek
Korzybski, Marek
This paper is focused on multiple soft fault diagnosis of linear time-invariant analog circuits and brings a method that achieves all objectives of the fault diagnosis: detection, location, and identification. The method is based on a diagnostic test arranged in the transient state, which requires one node accessible for excitation and two nodes accessible for measurement. The circuit is specified by two transmittances which express the Laplace transform of the output voltages in terms of the Laplace transform of the input voltage. Each of these relationships is used to create an overdetermined system of nonlinear algebraic equations with the circuit parameters as the unknown variables. An iterative method is developed to solve these equations. Some virtual solutions can be eliminated comparing the results obtained using both transmittances. Three examples are provided where laboratory or numerical experiments reveal effectiveness of the proposed method.
Electronics and Telecommunications Committee
2021-08-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137843
International Journal of Electronics and Telecommunications; Vol 67, No 3 (2021); 531-536
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137843/833
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137843/2849
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2407
2020-09-10T21:07:49Z
ijet:SIGNALS
Further Discussion on Modeling of Measuring Process via Sampling of Signals
Borys, Andrzej Marek
Measuring process; sampling of signals; smearing and averaging of signal samples
In this paper, we continue a topic of modeling measuring processes by perceiving them as a kind of signal sampling. And, in this respect, note that an ideal model was developed in a previous work. Whereas here, we present its nonideal version. This extended model takes into account an effect, which is called averaging of a measured signal. And, we show here that it is similar to smearing of signal samples arising in nonideal signal sampling. Furthermore, we demonstrate in this paper that signal averaging and signal smearing mean principally the same, under the conditions given. So, they can be modeled in the same way. A thorough analysis of errors related to the signal averaging in a measuring process is given and illustrated with equivalent schemes of the relationships derived. Furthermore, the results obtained are compared with the corresponding ones that were achieved analyzing amplitude quantization effects of sampled signals used in digital techniques. Also, we show here that modeling of errors related to signal averaging through the so-called quantization noise, assumed to be a uniform distributed random signal, is rather a bad choice. In this paper, an upper bound for the above error is derived. Moreover, conditions for occurrence of hidden aliasing effects in a measured signal are given.
Electronics and Telecommunications Committee
2020-09-07
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134006
International Journal of Electronics and Telecommunications; Vol 66, No 3 (2020); 507-513
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134006/726
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.134006/2233
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/425
2015-12-29T16:28:33Z
ijet:SIGNALS
Application for displaying synthetic aperture radar imagery in real-time Implementation and results
Borowiec, Krzysztof Ireneusz
SAR imagery; signal processing; real-time application
The paper presents implementation and results of the application for displaying SAR (Synthetic Aperture Radar) imagery operating in real-time. The application performs SAR imagery formation and displays results in real-time after receiving of preprocessed data via an SAR processing application. The application was used in SARape (Synthetic Aperture Radar for all weather penetrating UAV application) project founded by the European Defence Agency. The real-time operation is achieved thanks to implementation based on multithreading.
Electronics and Telecommunications Committee
2015-12-24
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0045
International Journal of Electronics and Telecommunications; Vol 61, No 4 (2015); 345-350
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0045/202
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/279
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/281
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/282
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/283
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/284
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/285
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/286
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/287
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/288
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/289
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/290
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/291
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/292
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/293
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/294
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/295
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/342
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/343
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0045/393
Copyright (c) 2015 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/4185
2023-07-31T01:06:51Z
ijet:SIGNALS
OTA Based Mem-capacitor Validation and Implementation Using Commercially Available IC
Shankar, Chandra
Nagar, Anuj
Singh, Ashutosh
Kumar, Ankleshwar
Memcapacitor; memristor; transconductance; mutator; tunable; hysteresis
This paper discusses a mem-capacitor circuit which is based on two MO-OTA along with a multiplier and 4 passive elements. This circuit is a charge-controlled memcapacitor emulator which is independent of any memristor also it consists the feature of electronic tunability. Additionally, this circuit is simpler and uses less hardware because it lacks a mutator and uses fewer active-passive components. The circuit behaviour is justified through various simulations in cadence Orcad tool with 180nm CMOS TSMC parameters. Additionally, conclusions from simulations and theory are validated experimentally through commercially available IC.
Electronics and Telecommunications Committee
No
2023-07-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.146511
International Journal of Electronics and Telecommunications; Vol 69, No 3 (2023); 587-592
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.146511/1133
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146511/4079
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146511/4127
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146511/4128
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146511/4129
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.146511/4130
Copyright (c) 2023 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1913
2019-10-21T18:07:30Z
ijet:SIGNALS
Smart Substation Network Fault Classification Based on a Hybrid Optimization Algorithm
Xia, Xin
Liu, Xiaofeng
Lou, Jichao
Accurate network fault diagnosis in smart substations is key to strengthening grid security. To solve fault classification problems and enhance classification accuracy, we propose a hybrid optimization algorithm consisting of three parts: anti-noise processing (ANP), an improved separation interval method (ISIM), and a genetic algorithm-particle swarm optimization (GA-PSO) method. ANP cleans out the outliers and noise in the dataset. ISIM uses a support vector machine (SVM) architecture to optimize SVM kernel parameters. Finally, we propose the GA-PSO algorithm, which combines the advantages of both genetic and particle swarm optimization algorithms to optimize the penalty parameter. The experimental results show that our proposed hybrid optimization algorithm enhances the classification accuracy of smart substation network faults and shows stronger performance compared with existing methods.
Electronics and Telecommunications Committee
2019-10-07
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129825
International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 657-663
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129825/625
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.129825/1489
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.129825/1490
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3284
2022-05-31T02:27:45Z
ijet:SIGNALS
A Comprehensive Review Of the Quadratic High Gain DC-DC Converter For Fuel Cell Application
Navamani, Divya
Pathi, Tanmay
Kumari, Aditi
sathik, Jagabar
In the recent times, lot of research work carried out in the field of fuel cells explicitly divulges that it has the potential to be an ultimate power source in upcoming years. The fuel cell has more storing capacity, which enables to use in heavy power applications. In these applications, power conditioning is more vital to regulate the output voltage. Hence, we need a dc-dc converter to provide a constant regulated output voltage for such high-power system. Currently, many new converters were designed and implemented as per the requirement. This paper has made comparative study on several topologies of the quadratic high gain dc-dc converter and the applications where these topologies can be used when the fuel cell is given as a source. Also, we have compared various parameters of all the converters considered and generated the results with steady-state and dynamic study. In this article, we briefed the types of analysis carried on the dc-dc converter to study its performance. Moreover, various application of fuel cell is presented and discussed. This paper will be a handbook to the researchers who start to work on high gain dc-dc converter topologies with quadratic boost converter as a base. This article will also guide the engineers to concentrate on the fuel cell components where it needs to be explored for optimizing its operation.
Electronics and Telecommunications Committee
2022-05-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139882
International Journal of Electronics and Telecommunications; Vol 68, No 2 (2022); 299-306
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139882/969
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139882/2778
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/751
2017-08-14T21:46:22Z
ijet:SIGNALS
A Modified Signal Feed-Through Pulsed Flip-Flop for Low Power Applications
Hassanzadeh, Alireza
Panahifar, Ehsan
Low power, Pulsed Flip-flop, Delay, Leakage power, Dynamic power
In this paper a modified signal feed-through pulsed flip-flop has been presented for low power applications. Signal feed-through flip-flop uses a pass transistor to feed input data directly to the output. Feed through transistor and feedback signals have been modified for delay, static and dynamic power reduction. HSPICE simulation shows 22% reduction in leakage power and 8% of dynamic power. Delay has been reduced by 14% using TSMC 90nm technology parameters. The proposed pulsed flip-flop has the lowest PDP (Power Delay Product) among other pulsed flip-flops discussed.
Electronics and Telecommunications Committee
2017-08-14
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0032
International Journal of Electronics and Telecommunications; Vol 63, No 3 (2017); 241-246
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0032/393
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/461
2016-03-30T07:27:52Z
ijet:SIGNALS
SMTBDD: New Form of BDD for Logic Synthesis
Kubica, Marcin
Kania, Dariusz
electronics; digital circuits
The main purpose of the paper is to suggest a new form of BDD – SMTBDD diagram, methods of obtaining, and its basic features. The idea of using SMTBDD diagram in the process of logic synthesis dedicated to FPGA structures is presented. The creation of SMTBDD diagrams is the result of cutting BDD diagram which is the effect of multiple decomposition. The essence of a proposed decomposition method rests on the way of determining the number of necessary ‘g’ bounded functions on the basis of the content of a root table connected with an appropriate SMTBDD diagram. The article presents the methods of searching non-disjoint decomposition using SMTBDD diagrams. Besides, it analyzes the techniques of choosing cutting levels as far as effective technology mapping is concerned. The paper also discusses the results of the experiments which confirm the efficiency of the analyzed decomposition methods.
Electronics and Telecommunications Committee
2016-03-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0004
International Journal of Electronics and Telecommunications; Vol 62, No 1 (2016); 33-41
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0004/234
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2016-0004/347
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2966
2021-05-11T08:41:30Z
ijet:SIGNALS
An overview of the methods of synthesis, realization and implementation of orthogonal 3-D rotation filters and possibilities of further research and development
Poczekajło, Paweł
DSP; digital filters, filters 3-D; orthogonal systems
In the paper, an overview of the methods and algorithms of synthesis, realization and implementation used by the author to obtain orthogonal 3-D filters with a structure made of Givens rotations has been presented. The main advantage of orthogonal filters, which may have a lower sensitivity to quantization of the coefficients, was indicated. The author proposed a number of possible changes and modifications of individual stages, which may result in obtaining filters with even better parameters. The work will be the basis for the direction of further research.
Electronics and Telecommunications Committee
2021-05-11
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135979
International Journal of Electronics and Telecommunications; Vol 67, No 2 (2021); 295-300
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135979/816
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135979/2436
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135979/2437
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135979/2723
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2311
2020-02-06T15:08:31Z
ijet:SIGNALS
A Solar-Powered Fertigation System based on Low-Cost Wireless Sensor Network Remotely Controlled by Farmer for Irrigation Cycles and Crops Growth Optimization
Visconti, Paolo
De Fazio, Roberto
Primiceri, Patrizio
Cafagna, Donato
Strazzella, Sergio
Giannoccaro, Nicola Ivan
precise farming; IoT devices; fertigation system; sensors; solar-powered WSN; data processing electronic boards
Nowadays, the technological innovations affect all human activities; also the agriculture field heavily benefits of technologies as informatics, electronic, telecommunication, allowing huge improvements of productivity and resources exploitation. This manuscript presents an innovative low cost fertigation system for assisting the cultures by using data-processing electronic boards and wireless sensors network (WSN) connected to a remote software platform. The proposed system receives information related to air and soil parameters, by a custom solar-powered WSN. A control unit elaborates the acquired data by using dynamic agronomic models implemented on a cloud platform, for optimizing the amount and typology of fertilizers as well as the irrigations frequency, as function also of weather forecasts got by on-line weather service.
Electronics and Telecommunications Committee
None
2020-02-06
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130266
International Journal of Electronics and Telecommunications; Vol 66, No 1 (2020); 59-68
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130266/681
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1701
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1702
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1703
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1704
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1705
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1706
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1707
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1708
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1709
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1710
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1711
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1712
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1713
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1714
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1715
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http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1717
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1718
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1719
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1720
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1721
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1722
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1723
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1724
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1725
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1726
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1727
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1728
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1729
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1730
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130266/1919
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/112
2014-09-30T17:52:02Z
ijet:SIGNALS
Square Root Raised Cosine Fractionally Delaying Nyquist Filter – Design and Performance Evaluation
Hermanowicz, Ewa
Rojewski, Mirosław
Signal Processing, Digital Filters
In this paper we propose a discrete-time FIR (Finite Impulse Response) filter which is meant to be applied as a square root Nyquist filter and fractional delay filter simultaneously. The filter enables to substitute for a cascade of square root raised cosine (SRRC) Nyquist filter and fractional delay filter in one device/algorithm. The aim is to compensate for transmission delay in digital communication system. Performance of the filter in the role of a matched filter is evaluated using a newly defined energetic ISI (Intersymbol Interference) measure and ability of the filter to completely eliminate the ISI involved by fractional delay of symbol shaping filter in transmitter or by channel delay. Considerations and results of the contribution are documented by suitable eye-diagrams and the SRRC filter responses.
Electronics and Telecommunications Committee
Faculty of Electronics, Telecommunications and Informatics
2014-09-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0031
International Journal of Electronics and Telecommunications; Vol 60, No 3 (2014); 247-252
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0031/40
oai:ojs.ijet.ise.pw.edu.pl:article/3604
2022-11-30T22:59:34Z
ijet:SIGNALS
Power-Ground Plane Impedance Modeling Using Deep Neural Networks and an Adaptive Sampling Process
Goay, Chan Hong
Cheong, Zheng Quan
Low, Chen Eng
Ahmad, Nur Syazreen
Goh, Patrick
adaptive sampling, deep neural networks, deep learning, power-ground plane, Z-parameters
This paper proposes a deep neural network (DNN) based method for the purpose of power-ground plane impedance modeling. A composite DNN model, which is a combination of two DNNs is used to predict the Z-parameters of power ground planes from their design parameters. The first DNN predicts the normalized Z-parameters whereas the second DNN predicts the original maximum and minimum values of the non-normalized Z-parameters. This allows the method to retain a high accuracy when predicting responses that have large variations across designs, as is the case with the Z-parameters of the power-ground planes. We use the adaptive sampling algorithm to generate the training and validation samples for the DNNs. The adaptive sampling algorithm starts with only a few samples, then slowly generates more samples in the non-linear regions within the design parameters space. The level of non-linearity of the regions is determined by a surrogate model which is also trained using the generated samples as well. If the surrogate model has poor prediction accuracy in a region, then the adaptive sampling algorithm will generate more samples in that region. A shallow neural network is used as the surrogate model for non-linearity determination of the regions since it is faster to train and update. Once all the samples have been generated, they will be used to train and validate the composite DNN models. Finally, we present two examples, a square-shaped power ground plane and a square-shaped power ground plane with a hollow square at the center to demonstrate the robustness of the DNN composite models.
Electronics and Telecommunications Committee
This work was supported by the Ministry of Higher Education, Malaysia, through the Fundamental Research Grant Scheme (FRGS) under Grant FRGS/1/2020/TK0/USM/02/7.
2022-11-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.143887
International Journal of Electronics and Telecommunications; Vol 68, No 4 (2022); 793-798
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.143887/1032
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.143887/3208
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.143887/3209
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1270
2018-07-20T19:13:02Z
ijet:SIGNALS
Mathematical model of calculating metric tensor and GNSS-observations errors taking into account relativistic effects
Bialyk, Ihor
Stepanchenko, Olha
Wójcik, Waldemar
Study of the trajectories of the motion of satellites remains an urgent task for modern science. This is especially true for GNSS systems and for satellites intended for Earth remote sensing. The basis of their operation is to accurately determine the position of the satellite, and the parameters of signal propagation. Considering the great distances and speeds of both satellites and the Earth in calculating these parameters, it is necessary to take into account the special and general theory of relativity. In the article formulas have been derived for calculating additional corrections for relativistic effects. A mathematical model for calculating the metric tensor was created. A sequence of correction was also proposed.
Electronics and Telecommunications Committee
2018-07-20
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-123536
International Journal of Electronics and Telecommunications; Vol 64, No 3 (2018); 379-384
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-123536/484
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3431
2021-08-31T09:43:27Z
ijet:SIGNALS
Extended Definitions of Spectrum of a Sampled Signal
Borys, Andrzej Marek
Signal Processing; Sampling
It is shown that a number of equivalent choices for the calculation of the spectrum of a sampled signal are possible. Two such choices are presented in this paper. It is illustrated that the proposed calculations are more physically relevant than the definition currently in use.
Electronics and Telecommunications Committee
2021-08-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137825
International Journal of Electronics and Telecommunications; Vol 67, No 3 (2021); 395-401
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137825/834
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137825/2948
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137825/2981
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/644
2016-09-23T21:08:11Z
ijet:SIGNALS
Understanding of Meyer and Stephens’s operator o as a multi-operational one
Borys, Andrzej Marek
Electronics; Circuits and Systems Theory
In this paper, the idea of an extended operator o introduced in the literature on modelling weakly nonlinear circuits by Meyer and Stephens is revisited. The mathematically precise definitions of this operator for the successive Volterra series terms are given. Furthermore, the exhaustive formal and illustrative descriptions of these definitions are also presented. Finally, the possibility of a reverse formulation for the convolution operations occurring in descriptions of weakly nonlinear circuits is reported.
Electronics and Telecommunications Committee
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0037
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 273-277
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0037/318
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/79
2015-12-29T16:37:50Z
ijet:SIGNALS
Instantaneous frequency estimation of multicomponent non- stationary signals using Fourier Bessel series and Time-Varying Auto Regressive Model
Gosula, Ravi Shankar Reddy
Rao, Rameshwar
In this paper, we propose a novel technique for Instantaneous frequency (IF) estimation of multi component non stationary signals using Fourier Bessel Series and Time–Varying Auto Regressive (FB-TVAR) model. In the proposed technique, the Fourier-Bessel (FB) expansion decomposes the multicomponent non stationary signal into a number of monocomponent signals and TVAR model is used to model each monocomponent signal. In TVAR modeling approach the time varying parameters are expanded as a linear combination of basis functions. In this paper, the TVAR parameters are expanded by a discrete cosine basis functions. The maximum likelihood estimation algorithm for model order selection in TVAR models is also discussed. The Instantaneous frequency (IF) is extracted from the time-varying parameters by calculating the angles of the estimation error filter polynomial roots. The estimation of the TVAR parameters of a multicomponent signal requires the inversion of a large covariance matrix, while the projected technique (FB-TVAR) requires the inversion of a number of comparatively small covariance matrices with better numerical stability properties. Simulation results are presented for three component discrete Amplitude and Frequency modulated(AM-FM)signal
Electronics and Telecommunications Committee
2015-12-24
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0048
International Journal of Electronics and Telecommunications; Vol 61, No 4 (2015); 365-376
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0048/214
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0048/396
Copyright (c) 2015 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2734
2020-11-22T18:22:53Z
ijet:SIGNALS
Frequency response testing of zero-sequence current transformers for mining ground fault protection relays
Kuliński, Krzysztof
Heyduk, Adam
zero-sequence current transformers; ground-fault protection relays; frequency response
W polskim górnictwie węgla sieci dystrybucyjne średniego napięcia działają z izolowanym punktem neutralnym. Przekładniki prądowe o zerowej sekwencji są podstawowymi czujnikami, które generują sygnały wejściowe dla przekaźników zabezpieczających przed zwarciem doziemnym. W literaturze problem analizy odpowiedzi częstotliwościowej różnych typów przekładników prądowych był wielokrotnie badany, np. [1] [2], ale jak dotąd nie dotyczy przekładników prądowych o zerowej sekwencji. W ramach pracy przetestowano dwa typy przekładników prądowych o zerowej sekwencji w zakresie od 0,1 Hz do 100 kHz. Przeanalizowano zarówno zmianę stosunku prądu, jak i przesunięcie kątowe między prądem wtórnym transformatora a całkowitym prądem pierwotnym.
Electronics and Telecommunications Committee
2020-11-22
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134030
International Journal of Electronics and Telecommunications; Vol 66, No 4 (2020); 701-705
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.134030/752
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.134030/2305
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.134030/2306
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/4418
2024-03-18T16:07:31Z
ijet:SIGNALS
Revision of the Formula Describing the Spectrum of Output Signals at A/D Converters
Borys, Andrzej Marek
Signal processing;
This paper crowns efforts, made by its author, aiming in showing and proving that the current formula for calculation of the spectra of output signals at A/D converters requires a correcting factor in it. A number of partial results obtained and published in the last years are referred to here. They paved the way to a fully satisfactory and correct result; it is presented in this work. The corrected formula for spectrum calculation is derived using a description of the output signal of an A/D converter by means of the so-called Dirac comb, however not in a direct form, but with taking into account physical reality. In addition, the paper contains a number of interpretative remarks, comments, and explanations - clarifying those matters that have so far been omitted in analyses of the sampling process, despite the fact that they raised various types of doubts.
Electronics and Telecommunications Committee
2024-03-18
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2024.149529
International Journal of Electronics and Telecommunications; Vol 70, No 1 (2024); 183-190
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2024.149529/1197
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2024.149529/4392
Copyright (c) 2024 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1959
2019-10-21T18:07:30Z
ijet:SIGNALS
Design and Testing of a Telemetry System Based on STM X-Nucleo Board for Detection and Wireless Transmission of Sensors Data Applied to a Single-Seat Formula SAE Car
Visconti, Paolo
Sbarro, Bernardo
Primiceri, Patrizio
de Fazio, Roberto
Ekuakille, Aimè Lay
telemetry; sensors; wireless monitoring; data communication; firmware; electronic modules
The emerged potentials and opportunities in the electronics field, which facilitate the creation of complex projects with innovative functionalities and high performances, while maintaining low costs, are becoming even more appreciated by designers, engineers and users. In this research work, a telemetry system was realized in order to monitor and control the principal physical and mechanical parameters of a racing vehicle by employing devices, available on the market, at very low cost. The used STM32 Nucleo development board, heart of realized telemetry system, properly programmed with the developed firmware, acquires data from sensors installed on vehicle and, by means of a WiFi module, sends them to a base station. A CAN module interfaces the engine control unit with the Nucleo board, allowing to control the engine parameters by proper sensors. All detected sensors data are both sent wirelessly and stored on a SD memory card for avoiding data losses and to implement a system robust and reliable. Experimental results show that all received data from base station are in accordance between themselves, reporting vehicle parameters for different driving and track conditions.
Electronics and Telecommunications Committee
2019-10-07
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130248
International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 671-678
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.130248/627
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1545
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1546
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1547
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1548
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1549
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1550
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1551
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1552
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1553
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1554
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1555
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1556
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1557
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1558
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1559
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1560
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1561
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2019.130248/1562
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3308
2022-03-08T12:08:31Z
ijet:SIGNALS
Optimizing the Bit-flipping Method for Decoding Low-density Parity-check Codes in Wireless Networks by Using the Artificial Spider Algorithm
Abdul-Adheem, Wameedh Riyadh
Ghaffoori, Ali Jasim
In this paper, the performance of Low-Density Parity-Check (LDPC) codes is improved, which leads to reduce the complexity of hard-decision Bit-Flipping (BF) decoding by utilizing the Artificial Spider Algorithm (ASA). The ASA is used to solve the optimization problem of decoding thresholds. Two decoding thresholds are used to flip multiple bits in each round of iteration to reduce the probability of errors and accelerate decoding convergence speed while improving decoding performance. These errors occur every time the bits are flipped. Then, the BF algorithm with a low-complexity optimizer only requires real number operations before iteration and logical operations in each iteration. The ASA is better than the optimized decoding scheme that uses the Particle Swarm Optimization (PSO) algorithm. The proposed scheme can improve the performance of wireless network applications with good proficiency and results. Simulation results show that the ASA-based algorithm for solving highly nonlinear unconstrained problems exhibits fast decoding convergence speed and excellent decoding performance. Thus, it is suitable for applications in broadband wireless networks.
Electronics and Telecommunications Committee
2022-02-26
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139857
International Journal of Electronics and Telecommunications; Vol 68, No 1 (2022); 109-114
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139857/935
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139857/2808
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139857/2809
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/428
2017-08-14T21:46:22Z
ijet:SIGNALS
Improved Gaussian mixture probability hypothesis density for tracking closely spaced targets
zhang, huanqing
Ge, Hongwei
Yang, Jinlong
signal processing;target tracking
Probability hypothesis density (PHD) filter is a suboptimal Bayesian multi-target filter based on random finite set. The Gaussian mixture PHD filter is an analytic solution to the PHD filter for linear Gaussian multi-target models. However, when targets move near each other, the GM-PHD filter cannot correctly estimate the number of targets and their states. To solve the problem, a novel reweighting scheme for closely spaced targets is proposed under the framework of the GM-PHD filter, which can be able to correctly redistribute the weights of closely spaced targets, and effectively improve the multiple target state estimation precision. Simulation results demonstrate that the proposed algorithm can accurately estimate the number of targets and their states, and effectively improve the performance of multi-target tracking algorithm.
Electronics and Telecommunications Committee
Jiangnan University,Internet of Things Engineering
2017-08-14
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0033
International Journal of Electronics and Telecommunications; Vol 63, No 3 (2017); 247-254
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0033/394
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/569
2016-09-08T11:39:19Z
ijet:SIGNALS
On Definition of Operator o for Weakly Nonlinear Circuits
Borys, Andrzej Marek
circuit theory; nonlinear circuits
For the first time, operator o appeared in the literature on weakly nonlinear circuits in a Narayanan’s paper on modelling transistor nonlinear distortion with the use of Volterra series. His definition was restricted only to the linear part of a nonlinear circuit description. Obviously, as we show here, Narayanan’s operator o had meaning of a linear convolution integral. The extended version of this operator, which was applied to the whole nonlinear circuit representation by the Volterra series, was introduced by Meyer and Stephens in their paper on modelling nonlinear distortion in variable-capacitance diodes. We show here that its definition as well as another definition communication to the author of this paper are faulty. We draw here attention to these facts because the faults made by Meyer and Stephens were afterwards replicated in publications of Palumbo and his coworkers on harmonic distortion calculation in integrated CMOS amplifiers, and recently in a paper about distortion analysis of parametric amplifier by H. Shrimali and S. Chatterjee. These faults are also present in some class notes for students, which are available on WWW-pages.
Electronics and Telecommunications Committee
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0034
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 253-259
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0034/315
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3060
2021-01-31T00:11:06Z
ijet:SIGNALS
Linearized 9-Bit Hybrid LBDD PWM Modulator for Digital Class-BD Amplifier
Kołodziejski, Wojciech
Kuta, Stanisław
The paper presents an original architecture andimplementation of 9-bit Linearized Pulse Width Modulator(LPWM) for Class-BD amplifier, based on the hybrid methodusing STM32 microcontroller and Programmable Tapped DelayLine (PTDL). The analog input signals are converted into 12-bitPCM signals, then are directly transformed into 32-bit LBDDDPWM data of the pulse-edge locations within n-th period of theswitching frequency, next requantized to the 9-bit digitaloutputs, and finally converted into the two physical trains of 1-bitPWM signals, to control the output stage of the Class-BD audioamplifier. The hybrid 9-bit quantizer converts 6 MSB bits usingcounter method, based on the peripherals of STM32microcontroller, while the remaining 3 LSB bits - using a methodbased on the PTDL. In the paper extensive verification ofalgorithm and circuit operation as well as simulation inMATLAB and experimental results of the proposed 9-bit hybridLBDD DPWM circuit have been performed. It allows to attainSNR of 80 dB and THD about 0,3% within the audio baseband.
Electronics and Telecommunications Committee
2021-01-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135943
International Journal of Electronics and Telecommunications; Vol 67, No 1 (2021); 49-57
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.135943/777
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.135943/2547
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2326
2021-08-28T17:49:50Z
ijet:SIGNALS
Some Topological Aspects of Sampling Theorem and Reconstruction Formula
Borys, Andrzej Marek
topological issues; reconstruction formula; sampling theorem;
In this paper, we present a few thoughts regarding topological aspects of transferring a signal of a continuous time into its discrete counterpart and recovering an analog signal from its discrete-time equivalent. In our view, the observations presented here highlight the essence of the above transform-ations. Moreover, they enable deeper understanding of the reconstruction formula and of the sampling theorem. We also interpret here these two borderline cases that are associated with a time quantization step going to zero, on the one hand, and approaching its greatest value provided by the sampling theorem, on the other.
Electronics and Telecommunications Committee
2020-06-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131878
International Journal of Electronics and Telecommunications; Vol 66, No 2 (2020); 301-307
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131878/696
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131878/821
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.131878/2209
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/195
2015-03-31T18:43:33Z
ijet:SIGNALS
New Synchronization Method for Transmission Systems with Variable Length of Bits
Godek, Juliusz
Golański, Ryszard
Kołodziej, Jacek
Stępień, Jacek
electronics; circutits and systems; delta modulation; adaptation; non-uniform sampling; synchronization; codec
Based on the Spartan 3E evaluation module, a flexible platform for the implementation of different algorithms for A/D conversion was developed. The aim of presented work was to improve the concept of the sampling rate adaptation to the input signal rate of change in terms of practical issues including synchronization of delta codecs. The new, original synchronization method, useful in systems dedicated for transmission of variable duration of bits was proposed and experimentally verified. Performed measures and observations have shown elimination of the synchronization lose phenomenon
Electronics and Telecommunications Committee
The work has been supported by AGH University of Science and Technology grant No 11.11.230.017
2015-03-16
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0004
International Journal of Electronics and Telecommunications; Vol 61, No 1 (2015); 31-36
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0004/84
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0004/105
oai:ojs.ijet.ise.pw.edu.pl:article/4049
2023-02-27T00:37:28Z
ijet:SIGNALS
An Unexpected Result on Modelling the Behavior of A/D Converters and the Signals They Produce
Borys, Andrzej Marek
signal sampling;signal processing
In this paper, we show that the signal sampling operation considered as a non-ideal one, which incorporates finite time switching and operation of signal blurring, does not lead, as the researchers would expect, to Dirac impulses for the case of their ideal behavior.
Electronics and Telecommunications Committee
2023-02-27
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.144350
International Journal of Electronics and Telecommunications; Vol 69, No 1 (2023); 193-198
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.144350/1075
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.144350/3952
Copyright (c) 2023 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/907
2018-07-20T19:13:02Z
ijet:SIGNALS
On Transformation of a Logical Circuit to a Circuit with NAND and NOR Gates Only
Baranov, Samary
Karatkevich, Andrei
logic synthesis; logic design; digital circuits
In the paper we consider fast transformation of amultilevel and multioutput circuit with AND, OR and NOT gatesinto a functionally equivalent circuit with NAND and NOR gates.The task can be solved by replacing AND and OR gates byNAND or NOR gates, which in some cases requires introducingthe additional inverters or splitting the gates. In the paper thequick approximation algorithms of the circuit transformation areproposed, minimizing number of the inverters. The presentedalgorithms allow transformation of any multilevel circuit into acircuit being a combination of NOR gates, NAND gates or bothtypes of universal gates.
Electronics and Telecommunications Committee
2018-07-20
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425123535
International Journal of Electronics and Telecommunications; Vol 64, No 3 (2018); 373-378
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425123535/483
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/741
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/742
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/743
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/744
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/745
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/746
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/747
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/748
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/749
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/750
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/751
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/752
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/753
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/754
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/954
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425123535/1253
Copyright (c) 2018 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3387
2022-05-31T02:27:45Z
ijet:SIGNALS
An Efficient Two-phase Clocked Sequential Multiply -Accumulator unit for Image blurring
Samanth, Rashmi
Nayak, Subramanya G.
Multiply-accumulator (MAC) unit; modified sequential multiplier;finite state machine (FSM); two-phase clocking; carry-save adder (CSA);image blurring.
The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 52% and improved the computation time by 4% than the conventional architectures. The developed MAC unit is implemented using 180nm standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB.
Electronics and Telecommunications Committee
2022-05-31
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139883
International Journal of Electronics and Telecommunications; Vol 68, No 2 (2022); 307-313
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139883/970
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139883/2909
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139883/2910
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/504
2016-09-08T11:39:19Z
ijet:SIGNALS
Heart-rate Monitoring System Design and Analysis Using a Nios II Soft-core Processor
Chun Keat, Lim
Bahari Jambek, Asral
Hashim, Uda
Pulse sensor; PPG; Heart rate; FPGA; Nios II
The heart rate of a person is able to tell whether they are healthy. A heart-rate monitoring device is able to measure or record the heart rate of a person in real time, whether it is an electrocardiogram (ECG) or a photoplethysmogram (PPG). In this work, a microprocessor system loaded with a heart-rate monitoring algorithm is implemented. The microprocessor system is the Nios II processor system, which interfaces with an analogue-to-digital converter (ADC) and a pulse sensor. A beat-finding algorithm is used in the microprocessor system for heart rate measurement. An experiment is carried out to analyse the functionality of the microprocessor system loaded with the algorithm. The results show that the detected heart rate is in the range of the average human being’s heart rate. The signal flow within the microprocessor system is observed and analysed using SignalTap II from Quartus’ software. Based on a power analysis report, the proposed microprocessor system has a total power dissipation of around 218.26 mW.
Electronics and Telecommunications Committee
Ministry of Higher Education, Malaysia.
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0039
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 283-288
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0039/304
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2016-0039/482
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/426
2016-01-19T08:01:52Z
ijet:SIGNALS
Passive radar parallel processing using General-Purpose computing on Graphics Processing Units
Szczepankiewicz, Karolina Barbara
Malanowski, Mateusz
Szczepankiewicz, Michał
Computer Science; Electronic Systems
In the paper an implementation of signal processing chain for a passive radar is presented. The passive radar which was developed at the Warsaw University of Technology, uses FM radio and DVB-T television transmitters as "illuminators of opportunity". As the computational load associated with passive radar processing is very high, NVIDIA CUDA technology has been employed for effective implementation using parallel processing. The paper contains the description of the algorithms implementation and the performance results analysis.
Electronics and Telecommunications Committee
2015-12-24
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0047
International Journal of Electronics and Telecommunications; Vol 61, No 4 (2015); 357-363
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0047/227
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0047/395
Copyright (c) 2015 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2939
2021-08-31T09:43:27Z
ijet:SIGNALS
Design of a Head Movement Navigation System for Mobile Telepresence Robot Using Open-source Electronics Software and Hardware
Jia Wee, Tan
Wahid, Herman
Telepresence; head movement control; real-time; video streaming; Bluetooth communication
Head movement is frequently associated with human motion navigation, and an indispensable aspect of how humans interact with the surrounding environment. In spite of that, the incorporation of head motion and navigation is more often used in the VR (Virtual Reality) environment than the physical environment. This study aims to develop a robot car capable of simple teleoperation, incorporated with telepresence and head movement control for an on-robot real-time head motion mimicking mechanism and directional control, in attempt to provide users the experience of an avatar-like third person’s point of view amid the physical environment. The design consists of three processes running in parallel; Motion JPEG (MJPEG) live streaming to html-Site via local server, Bluetooth communication, and the corresponding movements for the head motion mimicking mechanism and motors which acts in accordance to head motion as captured by the Attitude Sensor and apparent command issued by the user. The design serves its purpose of demonstration with the usage of basic components and is not aimed to provide nor research with regards to user experience.
Electronics and Telecommunications Committee
Universiti Teknologi Malaysia (UTM) and Ministry of Education (MOE) Malaysia
2021-08-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137823
International Journal of Electronics and Telecommunications; Vol 67, No 3 (2021); 379-384
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137823/831
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137823/2405
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2014
2019-10-21T18:07:30Z
ijet:SIGNALS
Impulse Noise Suppression Based on Power Iterative ICA in Power Line Communication
Zhang, Wei
Luo, Zhongqiang
Xiong, Xingzhong
To overcome the detrimental influence of impulse noise in power line communication and the trap of scarce prior information in traditional noise suppression schemes , a power iteration based fast independent component analysis (PowerICA) based noise suppression scheme is designed in this paper. Firstly, the pseudo-observation signal is constructed by weighted processing so that single-channel blind separation model is transformed into the multi-channel observed model. Then the proposed blind separation algorithm is used to separate noise and source signals. Finally, the effectiveness of the proposed algorithm is verified by experiment simulation. Experiment results show that the proposed algorithm has better separation effect, more stable separation and less implementation time than that of FastICA algorithm, which also improves the real-time performance of communication signal processing.
Electronics and Telecommunications Committee
2019-10-07
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129824
International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 651-656
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129824/624
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/71
2014-07-01T15:57:54Z
ijet:SIGNALS
A Stand-alone Station and DSP Method for Deep Sky Objects Astrophotography
Suszynski, Robert
Electronics
This article presents the basic assumptions and aspects of the design of a stand-alone station for deep sky objects (DSO) astrophotography. It describes the main elements of a project concerned with automatization, remote control and auto-guiding [1-5] of a system. The article also covers in further detail the innovative use of a driver with an ATMEGA16 microcontroller and dedicated software for controlling the astronomical dome and its synchronization with telescope movement. Furthermore, a new concept of reprogrammable digital circuit implementation for auto-guiding systems is shown, which operates with a popular CCD webcam and ST4 compatible equatorial mounts. This idea was verified by the circuit prototype implemented on an Altera Cyclone II FPGA device and tested with real sky objects. A fully functional solution for performing automatic observation is presented. The project was also designed for amateur-astronomy, and therefore, user-friendly configuration and maintenance constituted very important factors, which were taken into consideration.
Electronics and Telecommunications Committee
2014-06-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0019
International Journal of Electronics and Telecommunications; Vol 60, No 2 (2014); 157-164
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0019/25
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.2478-eletel-2014-0019/7
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.2478-eletel-2014-0019/8
oai:ojs.ijet.ise.pw.edu.pl:article/3594
2022-03-08T12:08:31Z
ijet:SIGNALS
Another Proof of Ambiguity of the Formula Describing Aliasing and Folding Effects in Spectrum of Sampled Signal
Borys, Andrzej Marek
signal processing; sampling
In this paper, a new proof of ambiguity of the formula describing the aliasing and folding effects in spectra of sampled signals is presented. It uses the model of non-ideal sampling operation published by Vetterli et al. Here, their model is modified and its black-box equivalent form is achieved. It is shown that this modified model delivers the same output sequences but of different spectral properties. Finally, a remark on two possible understandings of the operation of non-ideal sampling is enclosed.
Electronics and Telecommunications Committee
2022-02-26
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139858
International Journal of Electronics and Telecommunications; Vol 68, No 1 (2022); 115-122
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.139858/936
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139858/3197
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.139858/3224
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/769
2017-08-14T21:46:22Z
ijet:SIGNALS
Graphical Method of Reversible Circuits Synthesis
Skorupski, Andrzej
This paper presents a new approach to designing reversible circuits. Reversible circuits can decrease energy dissipation theoretically to zero. This feature is a base to build quantum computers. The main problem of reversible logic is designing optimal reversible circuits i.e. circuits with minimal gates number implementing the given reversible function. There are many types of reversible gates. Most popular library is a set of three types of gates so called CNT (Control, NOT and Toffoli). The method presented in this paper is based only on the Toffoli gates. A graphical representation of the reversible function called s-maps is introduced in the paper. This representation allows to find optimal reversible circuits. The paper is organized as follows. Section 1 recalls basic concepts of reversible logic. In Section 2 a graphical representation of the reversible functions is presented. Section 3 describes the algorithm whereby all optimal solutions of the given function could be obtained.
Electronics and Telecommunications Committee
2017-08-14
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0031
International Journal of Electronics and Telecommunications; Vol 63, No 3 (2017); 235-240
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0031/392
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0031/658
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0031/659
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0031/660
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0031/661
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0031/662
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/583
2016-09-08T11:39:19Z
ijet:SIGNALS
Operator o and analysis of harmonic distortion
Borys, Andrzej Marek
It has been shown that the description of mildly nonlinear circuits with the use of an operator o introduced by Meyer and Stephens in their paper published more than forty years ago was flawed. The problem now with their incorrect and imprecise definition is that it is still replicated in one or another form, as, for example, in publications of Palumbo and Pennisi on harmonic distortion calculation in integrated CMOS amplifiers or an article of Shrimali and Chatterjee on nonlinear distortion analysis of a three-terminal MOS-based parametric amplifier. Here, we discuss the versions of o operator presented in the works mentioned above and show points, where mistakes were committed. Also, we derive the correct forms of nonlinear circuit descriptions that should be used.
Electronics and Telecommunications Committee
2016-09-08
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0035
International Journal of Electronics and Telecommunications; Vol 62, No 3 (2016); 261-265
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2016-0035/316
Copyright (c) 2016 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2974
2021-08-31T09:43:27Z
ijet:SIGNALS
Two Optimization Ways of DDR3 Transmission Line Equal-Length Wiring Based on Signal Integrity
Cheng, Kaixing
Luo, Zhongqiang
Xiong, Xingzhong
Wei, Xiaohan
As we enter the 5G (5th-Generation) era, the amount of information and data has become increasingly tremendous. Therefore, electronic circuits need to have higher chip density, faster operating speed and better signal quality of transmission. As the carrier of electronic components, the design difficulty of high-speed PCB (Printed Circuit Board) is also increasing. Equal-length wiring is an essential part of PCB design. But now, it can no longer meet the needs of designers. Accordingly, in view of the shortcomings of the traditional equal-length wiring, this article proposes two optimization ways: the "spiral wiring" way and the "double spiral wiring" way. Based on the theoretical analysis of the transmission lines, the two optimization ways take the three aspects of optimizing the layout and wiring space, suppressing crosstalk and reducing reflection as the main points to optimize the design. Eventually, this article performs simulation and verification of schematic diagram and PCB of the optimal design by using HyperLynx simulation software. The simulation results show that these two ways not only improve the flexibility of the transmission line layout, but also improve the signal integrity of the transmission lines. Of course, this also proves the feasibility and reliability of the two optimized designs.
Electronics and Telecommunications Committee
2021-08-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137824
International Journal of Electronics and Telecommunications; Vol 67, No 3 (2021); 385-394
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137824/832
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137824/2445
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2339
2020-06-01T14:11:57Z
ijet:SIGNALS
Measuring Process via Sampling of Signals, and Functions with Attributes
Borys, Andrzej Marek
Measuring process; sampling of signals; functions with attributes; Dirichlet function;
In this paper, it has been shown that any measuring process can be modeled as a process of sampling of signals. Also, a notion of a special kind of functions, called here functions with attributes, has been introduced. The starting point here, in the first of the above themes, is an observation that in fact we are not able to measure and record truly continuously in time any physical quantity. The measuring process can be viewed as going stepwise that is in steps from one instant to another, similarly as a sampling of signals proceeds. Therefore, it can be modeled as the latter one. We discuss this in more detail here. And, the notion of functions with attributes, we introduced here, follows in a natural way from the interpretation of both the measuring process as well as the sampling of signals that we present in this paper. It turns out to be useful.
Electronics and Telecommunications Committee
2020-06-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131879
International Journal of Electronics and Telecommunications; Vol 66, No 2 (2020); 309-314
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2020.131879/697
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.131879/1778
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2020.131879/2210
Copyright (c) 2020 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/199
2015-07-31T22:49:45Z
ijet:SIGNALS
Synthesis of the magnetic field using transversal 3D coil system
Garda, Bartlomiej
Galias, Zbigniew
gradient coils, homogeneous magnet design, optimization
Magnetic field is usually generated using magnets realized as a set of simple coils. In general, those magnets generate magnetic field with nonzero components in all directions. Usually during the design process only one component of the magnetic field is taken into account, and in the optimisation procedure the currents and positions of simple coils are found to minimize the error between the axial component of the magnetic field and the required magnetic field in the ROI. In this work, it is shown that if the high quality homogeneous magnetic field is generated then indeed one may neglect non-axial components. On the other hand, if the obtained magnetic field is not homogeneous either due to design requirements of too restrictive constrains, then all other components may severely deteriorate the quality of the magnetic field. In the second part of the paper, we show how to design a 3D transversal coil system to solve problems which are intractable in the 1D case.
Electronics and Telecommunications Committee
AGH University of Science and Technology
2015-05-22
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/0.1515-eletel-2015-0027
International Journal of Electronics and Telecommunications; Vol 61, No 2 (2015); 205-210
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/0.1515-eletel-2015-0027/119
oai:ojs.ijet.ise.pw.edu.pl:article/4119
2023-05-18T20:31:22Z
ijet:SIGNALS
Sampled Signal Description That Is Used in Calculation of Spectrum of This Signal Needs Revision
Borys, Andrzej Marek
signal processing; telecommunications
In this paper, we show why the descriptions of the sampled signal used in calculation of its spectrum, that are used in the literature, are not correct. And this finding applies to both kinds of descriptions: the ones which follow from an idealized way of modelling of the signal sampling operation as well as those which take into account its non-idealities. The correct signal description, that results directly from the way A/D converters work (regardless of their architecture), is presented and dis-cussed here in detail. Many figures included in the text help in its understanding.
Electronics and Telecommunications Committee
2023-05-18
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.144367
International Journal of Electronics and Telecommunications; Vol 69, No 2 (2023); 319-324
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2023.144367/1098
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2023.144367/3965
Copyright (c) 2023 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1842
2019-09-01T21:32:26Z
ijet:SIGNALS
Some Useful Results Related with Sampling Theorem and Reconstruction Formula
Borys, Andrzej Marek
sampling theorem; cardinal series; reconstruction formula
In this paper, we present some useful results related with the sampling theorem and the reconstruction formula. The first of them regards a relation existing between bandwidths of interpolating functions different from a perfect-reconstruction one and the bandwidth of the latter. Furthermore, we prove here that two non-identical interpolating functions can have the same bandwidths if and only if their (same) bandwidth is a multiple of the bandwidth of an original unsampled signal. The next result shows that sets of sampling points of two non-identical (but not necessarily interpolating) functions possessing different bandwidths are unique for all sampling periods smaller or equal to a given period (calculated in a theorem provided). These results are completed by the following one: in case of two different signals possessing the same bandwidth but different spectra shapes, their sets of sampling points must differ from each other.
Electronics and Telecommunications Committee
2019-09-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129801
International Journal of Electronics and Telecommunications; Vol 65, No 3 (2019); 471-475
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129801/594
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/3364
2022-08-27T21:26:15Z
ijet:SIGNALS
Design of low–power 4-bit Flash ADC using Multiplexer based encoder in 90nm CMOS process
Sam, Shylu
Paul, Sam
Jingle, Diana Jeba
Paul, Mano
Samuel, Judith
J, Reshma
Sudeepa, Sarah
Evangeline, G
ECE,VLSI Design
This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence open-loop comparator and mux-based encoder are used to obtain improved performance. Simulation results shows that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and supply voltage of 1V.
Electronics and Telecommunications Committee
NIL
2022-08-27
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.141275
International Journal of Electronics and Telecommunications; Vol 68, No 3 (2022); 565-570
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2022.141275/1001
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.141275/3399
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2022.141275/3400
Copyright (c) 2022 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/540
2018-04-29T19:24:17Z
ijet:SIGNALS
Improved and innovated universal DAQ microcontroller unit
Dostálek, Petr
Pekař, Libor
Navrátil, Pavel
data acquisition card; engineering education; microcontroller unit; temperature control
This paper is aimed at the description of hardware design, software equipment and the functionality of the second evolution of the intelligent multipurpose input/output microcontroller converter and control unit designed and assembled by the authors. Preceding stages of the unit development are concisely overviewed first, the deficiencies of which give rise to the primary motivation of this contribution. Then separate hardware parts of the novel unit are described in detail including electronic schematic diagrams. The device firmware and software capabilities are introduced as well. The advantages of the unit are highlighted compared to older versions. Its functionality, performance and efficiency are then verified by a laboratory control-related dynamic responses measurement example. In the contrary to previous evolutions, a more compact hardware design, increased A/D and D/A converter resolutions, added USB communication capability, better and more accurate analog circuits with more advanced operation amplifiers, the use of OLED instead of LCD display, the pulse-width modulated signal generated by the microcontroller unit itself can be considered among the most important improvements. Moreover, the direct use of the serial link may reduce noise significantly and makes the device more universal.
Electronics and Telecommunications Committee
Ministry of Education, Youth and Sports of the Czech Republic
2017-04-18
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0023
International Journal of Electronics and Telecommunications; Vol 63, No 2 (2017); 171-180
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2017-0023/374
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0023/465
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2017-0023/567
Copyright (c) 2017 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/423
2015-12-29T16:31:53Z
ijet:SIGNALS
Efficient Two-Step Approach for Automatic Number Plate Detection
Gorovyi, Ievgen
intelligent transportation systems are rapidly growing mainly due to active development of novel hardware and software solutions. In the paper a problem of automatical number plate detection is considered. An efficient two-step approach based on plate candidates extraction with further classification by neural network is proposed. Stroke width transform and contours detection techniques are utilized for the image preprocessing and extraction of regions of interest. Different local feature sets are used for the final number plate extraction step. Efficiency of the developed method is tested with real datasets.
Electronics and Telecommunications Committee
2015-12-24
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0046
International Journal of Electronics and Telecommunications; Vol 61, No 4 (2015); 351-356
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.1515-eletel-2015-0046/203
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0046/276
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.1515-eletel-2015-0046/394
Copyright (c) 2015 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/2808
2021-12-19T22:22:33Z
ijet:SIGNALS
RFID-MA XTEA: Cost-Effective RFID-Mutual Authentication Design using XTEA Security on FPGA Platform
Anusha, R.
Shastrimath, V. Veena Devi
RFID systems are one of the essential technologies and used many diverse applications. The security and privacy are the primary concern in RFID systems which are overcome by using suitable authentication protocols. In this manuscript, the cost-effective RFID-Mutual Authentication (MA) using a lightweight Extended Tiny encryption algorithm (XTEA) is designed to overcome the security and privacy issues on Hardware Platform. The proposed design provides two levels of security, which includes secured Tag identification and mutual authentication. The RFID-MA mainly has Reader and Tag along with the backend Server. It establishes the secured authentication between Tag and Reader using XTEA. The XTEA with Cipher block chaining (CBC) is incorporated in RFID for secured MA purposes. The authentication process completed based on the challenge and response between Reader and Tag using XTEA-CBC. The present work is designed using Verilog-HDL on the Xilinx environment and implemented on Artix-7 FPGA. The simulation and synthesis results discussed with hardware constraints like Area, power, and time. The present work is compared with existing similar approaches with hardware constraints improvements.
Electronics and Telecommunications Committee
2021-12-01
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137855
International Journal of Electronics and Telecommunications; Vol 67, No 4 (2021); 623-629
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2021.137855/897
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137855/2470
http://ijet.pl/index.php/ijet/article/downloadSuppFile/10.24425-ijet.2021.137855/2974
Copyright (c) 2021 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/1752
2019-10-21T18:07:30Z
ijet:SIGNALS
CNTFET Based OTRA and its Application as Inverse Low Pass Filter
Prasad, Dinesh
Tayal, Divyam
Yadav, Ayesha
Singla, Laxya
Haseeb, Zainab
Carbon Nanotube (CNT), Operational Transresistance Amplifier (OTRA),
Operational Transresistance Amplifier (OTRA) has been a topic of great interest recently. OTRA has proved itself to be an appropriate device for the analog applications. As MOS scaling suffers from various problems, carbon nanotube field effect transistor (CNTFET) has came into light as one of the brightest alternative for FET (Field Effect Transistors) based devices. This work has introduced a new CNTFET based OTRA which is capable of realising inverse low pass filter using two OTRAs and few passive elements. CNTFET based OTRA has been designed and simulated at 10nm technology node. The working ability of the designed model has been conformed using HSPICE simulation. It is compared with conventional CMOS based OTRA. The comparative analysis has revealed improvement in various performance parameters. The paper also presents how change in number of carbon nanotube in CNTFETs in OTRA circuit affects the transresistance gain and input impedance. The optimized results are also discussed to improve transresistance gain and input impedance. The paper also dealt with the realisation of inverse low pass filter using proposed CNTFET based OTRA.
Electronics and Telecommunications Committee
Young faculty research felloship, MEITY, delhi
2019-10-07
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129826
International Journal of Electronics and Telecommunications; Vol 65, No 4 (2019); 665-670
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.24425-ijet.2019.129826/626
Copyright (c) 2019 International Journal of Electronics and Telecommunications
oai:ojs.ijet.ise.pw.edu.pl:article/48
2014-07-01T15:57:54Z
ijet:SIGNALS
Nonlinear Optimal Tracking For Missile Gimbaled Seeker Using Finite-Horizon State Dependent Riccati Equation
Khmais, Ahmed
Kamel, Ahmed
Naidu, D. Subbaram
Optimal control; nonolinear tracking
The majority of homing guided missiles use gimbaled seekers. The equations describing seeker gimbal system are highly nonlinear. Accurate nonlinear control of the motion of the gimbaled seeker through the attached DC motors is required. In this paper, an online technique for finite-horizon nonlinear racking problems is presented. The idea of the proposed technique is the change of variables that converts the nonlinear differential Riccati equation to a linear Lyapunov differential equation. The proposed technique is effective for wide range of operating points. Simulation results for a realistic gimbaled system with different engagement scenarios are given to illustrate the effectiveness of the proposed technique.
Electronics and Telecommunications Committee
2014-06-30
info:eu-repo/semantics/article
info:eu-repo/semantics/publishedVersion
application/pdf
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0020
International Journal of Electronics and Telecommunications; Vol 60, No 2 (2014); 165-171
2300-1933
eng
http://ijet.pl/index.php/ijet/article/view/10.2478-eletel-2014-0020/26