Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold
Abstract
Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node as
the application of the proposed model.
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