Fixed-latency system for high-speed serial transmission between FPGA devices with Forward Error Correction
Abstract
This paper presents the design of a compact pro-
tocol for fixed-latency, high-speed, reliable, serial transmission
between simple field-programmable gate arrays (FPGA) devices.
Implementation of the project aims to delineate word boundaries,
provide randomness to the electromagnetic interference (EMI)
generated by the electrical transitions, allow for clock recov-
ery and maintain direct current (DC) balance. An orthogonal
concatenated coding scheme is used for correcting transmission
errors using modified Bose–Chaudhuri–Hocquenghem (BCH)
code capable of correcting all single bit errors and most of
the double-adjacent errors. As a result all burst errors of a
length up to 31 bits, and some of the longer group errors,
are corrected within 256 bits long packet. The efficiency of the
proposed solution equals 46.48%, as 119 out of 256 bits are
fully available to the user. The design has been implemented
and tested on Xilinx Kintex UltraScale+ KCU116 Evaluation Kit
with a data rate of 28.2 Gbps. Sample latency analysis has also
been performed so that user could easily carry out calculations
for different transmission speed. The main advancement of the
work is the use of modified BCH(15, 11) code that leads to high
error correction capabilities for burst errors and user friendly
packet length.
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