Performance Comparison of Stacked Dual-Metal Gate Engineered Cylindrical Surrounding Double-Gate MOSFET

Authors

Abstract

In this research work, a Cylindrical Surrounding Double-Gate (CSDG) MOSFET design in a stacked-Dual Metal Gate (DMG) architecture has been proposed to incorporate the ability of gate metal variation in channel field formation. Further, the internal gate's threshold voltage (VTH1) could be reduced compared to the external gate (VTH2) by arranging the gate metal work-function in Double Gate devices. Therefore, a device design of CSDG MOSFET has been realized to instigate the effect of Dual Metal Gate (DMG) stack architecture in the CSDG device. The comparison of device simulation shown optimized electric field and surface potential profile. The gradual decrease of metal work function towards the drain also improves the Drain Induced Barrier Lowering (DIBL) and subthreshold characteristics. The physics-based analysis of gate stack CSDG MOSFET that operates in saturation involving the analogy of cylindrical dual metal gates has been considered to evaluate the performance improvements. The insights obtained from the results using the gate-stack dual metal structure of CSDG are quite promising, which can serve as a guide to further reduce the threshold voltage roll-off, suppress the Hot Carrier Effects (HCEs) and Short Channel Effects (SCEs).

Author Biographies

Abha Dargar, Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban South Africa

ABHA DARGAR received her Master’s degree (2014) in Digital Communication and Bachelor degree (2009) in Electronics and Communication Engineering. She is currently pursuing her Ph.D. in the Electronics Engineering at Howard College, University of KwaZulu-Natal, Durban, South Africa. Her research interest includes device design, circuit modeling, Microelectronics, VLSI, wireless communication, Microwave and Communication Engineering. She authored/co-authored various scientific contributions including articles in international refereed journals, and IEEE conferences. She is member of IEEE and IEEE Women in Engineering.

Viranjay M. Srivastava, Department of Electronic Engineering, Howard College, University of KwaZulu-Natal, Durban South Africa

VIRANJAY M. SRIVASTAVA received his Ph.D. degree (2012) in the field of RF Microelectronics and VLSI design, Master’s (2008) in VLSI design, and Bachelor (2002) in Electronics and Instrumentation Engineering. He has worked for the fabrication of devices and development of the circuit design. Presently, he is working as an Associate Professor in the department of electronic engineering, Howard College, University of KwaZulu-Natal, Durban, South Africa. He has more than 18 years of teaching and research experience in the area of VLSI design, RFIC design, and analog IC design. He has supervised various Bachelors, Masters and Doctoral research. He is a Professional Engineer (ECSA), South Africa, senior member of IEEE, SAIEE and member of IET, IEEE-HKN, IITPSA. He authored/co-authored more than 240 scientific contributions including articles in international refereed journals, chapters in book, and conferences.

References

G. E. Moore, “Cramming more components into integrated circuit,” Reprinted from Electronics, vol. 38, no. 8, April 19, 1965, p. 114 in IEEE solid-state circuits society newsletter, vol. 11, no. 3, pp. 33-35, 2006. DOI: 10.1109/N-SSC.2006.4785860.

K. Roy, K. S. Yeo, “Low voltage, low power VLSI subsystems,” New York: McGraw-Hill, 2005.

A. Kahn, “Fermi level, work function and vacuum level,” Materials Horizons, vol. 3, no. 1, pp. 7-10, Oct. 2015. DOI: 10.1039/C5MH00160A

A. Dargar and V. M. Srivastava, “Thickness modeling of short-channel cylindrical surrounding double-gate MOSFET at strong inversion using depletion depth analysis,” Micro and Nanosystems, vol. 12, no. 1, September 2020. DOI: 10.2174/1876402912666200831175936.

S. Deb, B. N. Singh, N. Islam, and S. K. Sarkar, “Work function engineering with linearly graded binary metal alloy gate electrode for short-channel SOI MOSFET,” IEEE Transactions on Nanotechnology, vol. 11, no. 3, pp. 472-478, 2011. DOI: 10.1109/TNANO.2011.2177669

T. K. Chiang and M. L. Chen, “A new two-dimensional analytical model for short-channel symmetrical dual-material double-gate metal–oxide–semiconductor field effect transistors,” Japanese Journal of Applied Physics, vol. 46, no. 6A, p. 3283-3290, 2007.

Y. H. Shin, M. S. Bae, C. Park, J. W. Park, H. Park, Y. J. Lee, and I. Yun, “Universal core model for multiple-gate field-effect transistors with short channel and quantum mechanical effects,” Semiconductor Science and Technology, vol. 33, no. 6, pp. 065010(1-8), 2018.

T. Kim, N. Franklin, C. Srinivasan, P. Kalavade, and A. Goda, “Extreme short-channel effect on RTS and inverse scaling behavior: source–drain implantation effect in 25-nm NAND Flash memory,” IEEE electron device letters, vol. 32, no. 9, pp. 1185-1187, 2011.

J. P. Colinge, “Multiple gate SOI MOSFETs,” Solid State Electron, vol. 48, no. 6, pp. 897-905, 2004.

V. M. Srivastava, K. S. Yadav, and G. Singh, “Design and performance analysis of cylindrical surrounding double-gate MOSFET for RF switch,” Microelectronics Journal, vol. 42, no. 10, pp. 1124-1135, 2011.

L. Naidoo and V. M. Srivastava, “Application of CSDG MOSFET based active high pass filter in satellite communications: A circuit perspective,” International Conference on Advances in Big Data, Computing and Data Communication Systems, 6-7 Aug. 2018, Durban, South Africa, pp. 1-5.

S. Baishya, A. Mallik, and C. K. Sarkar, “A pseudo two-dimensional subthreshold surface potential model for dual-material gate MOSFETs,” IEEE Transactions on Electron Devices, vol. 54, no. 9, pp. 2520-2525, 2007.

T. G. James, S. Joseph, and V. Mathew, “The Influence of Metal Gate Work Function on Short Channel Effects in Atomic-layer Doped DG MOSFETs,” Journal of Electron Devices, vol. 8, pp. 310-319, 2010.

P. Ghosh, S. Haldar, R. S. Gupta, and M. Gupta, “Analytical modeling and simulation for dual metal gate stack architecture cylindrical/surrounded gate MOSFET,” Journal of semiconductor Technology and Science, vol. 12, no. 4, pp. 458-466, 2012.

S. K. Mohapatra, K. Pradhan, P. K. Sahu, and M. R. Kumar, “The performance measure of GS-DG MOSFET: an impact of metal gate work function,” Advances in Natural Sciences: Nanoscience and Nanotechnology, vol. 5, no. 2, pp. 025002, 2014.

F. Lagraf, R. Djamil, G. Kamel, and Z. Mourad, “Channel length effect on subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs with High-k Gate Dielectrics,” Journal of Nano and Electronic Physics, vol. 11, no. 2, 2019. DOI: 10.21272/jnep.11(2).02011

M. R. Hasan, K. Ullah, M. Hossain, T. Hossain, N. F. Rashid, S. Quraishi, and P. Ghosh, “Metal gate work function engineering: sub-nano regime double date MOSFETs,” International Conference on Electrical, Computer and Communication Engineering, CoxsBazar, Bangladesh, 7-9 February 2019, pp. 1-5. DOI:10.1109/ECACE.2019.8679134

Y. B. Kim, Challenges for nanoscale MOSFETs and emerging nano-electronics, Trans. on Electrical and Electronic Materials, Vol. 11, 93-105, 2010. DOI: 10.4313/TEEM.2010.11.3.093.

F. Chaves, D. Jimenez, and J. Sune, “Explicit model for the gate tunneling current in double-gate MOSFETs, Solid-State Electronics, vol. 68, pp. 93-97, 2012. DOI: 10.1016/j.sse.2011.11.003

A. Martinez, M. Aldegunde, N. Seoane, A. R. Brown, J. R. Barker, and A. Asenov, “Quantum-transport study on the impact of channel length and cross-sections on variability induced by random discrete dopants in narrow gate-all-around silicon nanowire transistors, IEEE Transaction of Electron Devices, vol. 58, pp. 2209- 2217, 2011.DOI: 10.1109/TED.2011.2157929

Downloads

Published

2024-04-19

Issue

Vol. 67 No. 1 (2021)

Section

Microelectronics, nanoelectronics

License

Copyright (c) 2021 International Journal of Electronics and Telecommunications

Creative Commons License

This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

1. License

The non-commercial use of the article will be governed by the Creative Commons Attribution license as currently displayed on https://creativecommons.org/licenses/by/4.0/.

2. Author’s Warranties

The author warrants that the article is original, written by stated author/s, has not been published before, contains no unlawful statements, does not infringe the rights of others, is subject to copyright that is vested exclusively in the author and free of any third party rights, and that any necessary written permissions to quote from other sources have been obtained by the author/s. The undersigned also warrants that the manuscript (or its essential substance) has not been published other than as an abstract or doctorate thesis and has not been submitted for consideration elsewhere, for print, electronic or digital publication.

3. User Rights

Under the Creative Commons Attribution license, the author(s) and users are free to share (copy, distribute and transmit the contribution) under the following conditions: 1. they must attribute the contribution in the manner specified by the author or licensor, 2. they may alter, transform, or build upon this work, 3. they may use this contribution for commercial purposes.

4. Rights of Authors

Authors retain the following rights:

- copyright, and other proprietary rights relating to the article, such as patent rights,

- the right to use the substance of the article in own future works, including lectures and books,

- the right to reproduce the article for own purposes, provided the copies are not offered for sale,

- the right to self-archive the article

- the right to supervision over the integrity of the content of the work and its fair use.

5. Co-Authorship

If the article was prepared jointly with other authors, the signatory of this form warrants that he/she has been authorized by all co-authors to sign this agreement on their behalf, and agrees to inform his/her co-authors of the terms of this agreement.

6. Termination

This agreement can be terminated by the author or the Journal Owner upon two months’ notice where the other party has materially breached this agreement and failed to remedy such breach within a month of being given the terminating party’s notice requesting such breach to be remedied. No breach or violation of this agreement will cause this agreement or any license granted in it to terminate automatically or affect the definition of the Journal Owner. The author and the Journal Owner may agree to terminate this agreement at any time. This agreement or any license granted in it cannot be terminated otherwise than in accordance with this section 6. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.

7. Royalties

This agreement entitles the author to no royalties or other fees. To such extent as legally permissible, the author waives his or her right to collect royalties relative to the article in respect of any use of the article by the Journal Owner or its sublicensee.

8. Miscellaneous

The Journal Owner will publish the article (or have it published) in the Journal if the article’s editorial process is successfully completed and the Journal Owner or its sublicensee has become obligated to have the article published. Where such obligation depends on the payment of a fee, it shall not be deemed to exist until such time as that fee is paid. The Journal Owner may conform the article to a style of punctuation, spelling, capitalization and usage that it deems appropriate. The Journal Owner will be allowed to sublicense the rights that are licensed to it under this agreement. This agreement will be governed by the laws of Poland.

By signing this License, Author(s) warrant(s) that they have the full power to enter into this agreement. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.