Lightweight PUF-Based Gate Replacement Technique to Reduce Leakage of Information through Power Profile Analysis

Authors

  • N Mohankumar Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Amritanagar, Coimbatore, Tamil Nadu - 641112, India http://orcid.org/0000-0002-0704-7632
  • M Jayakumar Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India
  • Devi M Nirmala Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India

Abstract

The major challenge faced by electronic device designers is to defend the system from attackers and malicious modules called Hardware Trojans and to deliver a secured design. Although there are many cryptographic preventive measures in place adversaries find different ways to attack the device. Differential Power Analysis (DPA) attack is a type of Side Channel Attacks, used by an attacker to analyze the power leakage in the circuit, through which the functionality of the circuit is extracted. To overcome this, a lightweight approach is proposed in this paper using, Wave Dynamic Differential Logic (WDDL) technique, without incurring any additional resource cost and power. The primary objective of WDDL is to make the power consumption constant of an entire circuit by restricting the leakage power. The alternate strategy used by an adversary is to leak the information through reverse engineering. The proposed work avoids this by using a bit sequencer and a modified butterfly PUF based randomizing architecture. A modified version of butterfly PUF is also proposed in this paper, and from various qualitative tests performed it is evident that this PUF can prevent information leakage. This work is validated on ISCAS 85, ISCAS 89 benchmark circuits and the results obtained indicate that the difference in leakage power is found to be very marginal.

Author Biographies

N Mohankumar, Department of Electronics and Communication Engineering, Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Amritanagar, Coimbatore, Tamil Nadu - 641112, India

Presently Mohankumar N. is serving as an Assistant Professor in the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore, India. He received his Master of Technology in Microelectronics and VLSI Design from the National Institute of Technology Calicut (NITC) in 2008 and a Bachelor of Engineering in Electronics and Communication Engineering from Amrita Institute of Technology and Science (affiliated to Bharathiar University, Coimbatore) in 2004. Presently he is pursuing his research in the area of Hardware Security and Trust.

His research interests include Design for Security, Hardware Security & Trust, Digital IC Design, Biologically Inspired Computing Techniques. He has authored more than 40 technical publications in national and international journals and conferences. 

M Jayakumar, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India

Dr. Jayakumar joined Amrita Vishwa Vidyapeetham in July 2004 after serving in satellite communication industries for eight years. His area of research includes, radio frequency systems, antennas, RF integrated circuits and wireless communication systems.

Dr. Jayakumar obtained his PhD from the University of Delhi in 1996 in the area of Microwave planar components and circuits using high temperature superconducting materials. Most of his experimental works were carried out in National Physical Laboratory, New Delhi mainly adopting indigenously developed high temperature superconducting materials. As a part of his research work he has developed a Novel Cavity Resonator operating at 24GHz based measurement system to measure the electromagnetic properties of high temperature superconducting thin films and bulk samples. This fetched him to get the IEEE student award in one of the IEEE conference (IEEE – InterMag –MMM – 1994) in Albuquerque, New Mexico, USA. He was awarded Dr. K.S. Krishnan Research Fellowship by the department of Atomic Energy (DAE) in Engineering Science during his research work. He started his professional career in teaching and research from Thapar University Patiala for a brief period. Currently he is a Professor and Chairperson of the Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore

Devi M Nirmala, Department of Electronics and Communication Engineering, Amrita School of Engineering, Coimbatore, Amrita Vishwa Vidyapeetham, India

Dr. M. Nirmala Devi obtained her B.E. degree in Electronics and Communication Engineering (ECE) in 1990 and M. E. (Applied Electronics) Degree in 1996 from Government College of Technology, Coimbatore, Bharathiar University. She is currently working as the Professor in Amrita School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore. During her tenure at Amrita, she received her Ph. D. degree in the area of VLSI Design of Artificial Neural Networks from Anna University, Chennai in 2010. She has been the coordinator for M. Tech. VLSI Design program. Her areas of interest include VLSI Design and Testing, Computational Intelligence, Hardware Security and Trust, Evolvable Hardware and RF CMOS System Design. She has published around 55 papers in the International Journals and Conferences in her field of expertise.

References

Swarup Bhunia., Michael S. Hsiao., Mainak Banga., Seetharam Narasimhan. (2014.): Hardware Trojan Attacks: Threat Analysis and Countermeasures. In: Proceedings of IEEE, Vol.102, No.8. DOI: 10.1109/JPROC.2014.2334493

Masoud Rostami., Farinaz Koushanfar., and Ramesh Karri.(2014.): A Primer on Hardware Security: Models,Methods, and Metrics. In: Proceedings of IEEE, Vol.102, No.8. DOI: 10.1109/JPROC.2014.2335155

Seetharam Narasimhan., Rajat Subhra Chakraborty., Swarup Chakraborty.(2012) Hardware IP Protection During Evaluation Using Embedded Sequential Trojan. In: IEEE Design and Test of Computers, Vol.29, pp. 70-79. DOI: 10.1109/MDT.2012.2205997

Yier Jin., Nathan Kupp., and Yiorgos Makris.(2009) Experiences in Hardware Trojan Design and Implementation. In: IEEE International Workshop On Hardware-Oriented Security and Trust, pp 50-57. DOI: 10.1109/HST.2009.5224971

Yuyu Zhang., Guoxi Wang., Yufeng Ma., Jingwen Li. (2011) A Comprehensive Design Method Based on WDDL and Dynamic Cryptosystem to Resist DPA Attack. In: International Conference on Intelligence Science and Information Engineering, pg. 333-336. DOI: 10.1109/ISIE.2011.145

Nianhao Zhu., Yujie Zhou., and Hongming Liu.( 2015) A Novel Way to Implement WDDL Logic to Resist Power Analysis Attack in Algorithm Level. In: Applied Mathematics and Information Sciences, Vol.9, No. 1, pg. 269-280. DOI:10.12785/amis/010133

Zhimin Chen., Ambuj Sinha., and Patrick Schaumont.(2013) Using Virtual Secure Circuit to Protect Embedded Software from Side-Channel Attacks. In: IEEE Transactions on Computers, Vol. 62, No. 1. DOI: 10.1109/TC.2011.225. DOI: 10.1109/TC.2011.225

Behnam Khaleghi., Ali Ahari., Hossein Asadi., and Siavash Bayat-Sarmadi.(2015) FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic. In: IEEE Embedded Systems Letters, Vol. 7, No. 2. DOI: 10.1109/LES.2015.2406791

Yier Jin., Xiaolong Guo., Raj Gautam Dutta., Mohammad-Mahdi Bidmeshki., Yiorgos Makris (2017) Data Secrecy Protection Through Information Flow Tracking in Proof-Carrying Hardware IP Part I: Framework Fundamentals. In: IEEE Transactions on Information Forensics And Security, Vol. 12, No. 10. DOI: 10.1109/TIFS.2017.2707323

Tushar Singh Chouhan (2015) Implementation of PRESENT Cryptographical Algorithm for the Encryption of Messages in NETFPGA. In: International Conference on Computational Intelligence and Communication Networks, pg. 1115-1119. DOI: 10.1109/CICN.2015.219

Massimo Alioto., Massimo Poli., and Santina Rocch (2010) A General Power Model of Differential Power Analysis Attacks to Static Logic Circuits. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 18, No. 5. DOI: 10.1109/TVLSI.2009.2015327

N. Avirneni., and A. Somani (2013) Countering Power Analysis Attacks using Reliable and Aggressive Designs. In: IEEE Transactions on Computers, pg. 1-10. DOI: 10.1109/TC.2013.9

Xiaoming Chen., Qiaoyi Liu., Yu Wang., Qiang Xu., and Huazhong Yang (2017) Low-Overhead Implementation of Logic Encryption Using Gate Replacement Techniques. In: 18th International Symposium on Quality Electronic Design (ISQED), pg. 257-263. DOI: 10.1109/ISQED.2017.7918325

Shiva Prasad R, Anirudh Siripagada., Santthosh Selvaraj., Mohankumar N(2018) “Random Seeding LFSR based TRNG for Hardware Security Applications” In: Second International Conference on Integrated Intelligent Computing, Communication and Security(ICIIC). DOI:10.1007/978-981-10-8797-4-44.

Ali Sadr., Mostafa Zolfaghari-Nejad (2012) Physical Unclonable Function (PUF) Based Random Number Generator. In: Advanced Computing: An International Journal ( ACIJ ), Vol.3, No.2.

Abhranil Maiti., Raghunandan Nagesh., Anand Reddy., Patrick Schaumont(2009) Physical Unclonable Function and True Random Number Generator: a Compact and Scalable implementation. In: the 19th ACM Great Lakes symposium on VLSI. https://doi.org/10.1145/1531542.1531639

Kumar, A.V., Bharathi, S., Meghana, C., Anusha, K., & Priyatharishini, M. (2019). Toggle Count Based Logic Obfuscation. 2019 3rd International conference on Electronics, Communication and Aerospace Technology (ICECA), 809-814. DOI: 10.1109/ICECA.2019.8821935

V. A. Deepak, M. Priyatharishini, M. Nirmala Devi (2019)", Design Protection Using Logic Encryption and Scan-Chain Obfuscation Techniques", International Journal of Electronics and Telecommunications, Volume 65, Issue 3, Pages 389 – 396. DOI: 10.24425/ijet.2019.129790

S. Sankaran, S. Shivshankar and K. Nimmy,(2018),"LHPUF: Lightweight Hybrid PUF for Enhanced Security in Internet of Things," 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp. 275-278, doi: 10.1109/iSES.2018.00066.

A. Cui, C. H. Chang, W. Zhou and Y. Zheng, (2021), "A New PUF Based Lock and Key Solution for Secure In-field Testing of Cryptographic Chips," in IEEE Transactions on Emerging Topics in Computing, vol. 9, no. 2, pp. 1095-1105, doi: 10.1109/TETC.2019.2903387.

U. Rührmair and M. van Dijk, (2013), "PUFs in Security Protocols: Attack Models and Security Evaluations," 2013 IEEE Symposium on Security and Privacy, Berkeley, CA, pp. 286-300, doi: 10.1109/SP.2013.27.

Krzysztof Szczypiorski (2020) "Cyber(in)security", International Journal of Electronics and Telecommunications, Volume 66, Issue 1, Pages 243-248. DOI: 10.24425/ijet.2020.131870

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Published

2024-04-19

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Section

Security, Safety, Military