ADC Emulation on FPGA

Authors

  • Huma Tabassum RV College of Engineering
  • Krishna Prathik BV RV College of Engineering
  • Sujatha S Hiremath RV College of Engineering

Abstract

Analog-to-Digital Converters (ADCs) are devices that transform analog signals into digital signals and are used in various applications such as audio recording, data acquisition, and measurement systems [1]. Prior to the development of actual chip, there is a need for prototyping, testing and verifying the performance of ADCs in different scenarios. Analog macros cannot be tested on an FPGA. In order to ensure the macros function properly, the emulation of the ADC is done first. This is a digital module and can be designed in System Verilog. This paper demonstrates the design of the module on FPGA for Analog to Digital Converter (ADC) emulation. The emulation is done specific to the ADC macro which has programmable resolutions of 12, 10, 8 or 6 bits. To validate the simulation results, the designed module is tested on FPGA. The outputs and logic block utilization are analyzed. The number of LUTs utilized in the design is 38, the number of flip flops needed is 41 and the input output pin utilization is 20. The dynamic power utilization of the design is 0.543W and the static power utilization is 0.082W.

Author Biography

Sujatha S Hiremath, RV College of Engineering

Assistant Professor, Electronics and Communication

RV College of Engineering

References

S. Pavan and H. Shibata, "Continuous-Time Pipelined Analog-to-Digital

Converters: A Mini-Tutorial," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 68, no. 3, pp. 810-815, March 2021, doi:

1109/TCSII.2020.3048850.

Y. Hu, K. Yan and W. Jing, "Design of ADC Control Module in a MCU,"

Fourth International Conference on Natural Computation, Jinan,

China, 2008, pp. 133-137, doi: 10.1109/ICNC.2008.204.5

C. Sapsanis, M. Villemur and A. G. Andreou, "Real Number Modeling

of a SAR ADC behavior using SystemVerilog," 2022 18th International

Conference on Synthesis, Modeling, Analysis and Simulation Methods

and Applications to Circuit Design (SMACD), Villasimius, Italy, 2022,

pp. 1-4, doi: 10.1109/SMACD55068.2022.9816309.

G. G. E. Gielen, L. Hernandez and P. Rombouts, "Time-Encoding Analogto-Digital Converters: Bridging the Analog Gap to Advanced Digital

CMOS-Part 1: Basic Principles," in IEEE Solid-State Circuits Magazine,

vol. 12, no. 2, pp. 47-55, Spring 2020, doi: 10.1109/MSSC.2020.2987536.

S. Bashir, S. Ali, S. Ahmed and V. Kakkar, "Analog-to-digital

converters: A comparative study and performance analysis," 2016

International Conference on Computing, Communication and Automation (ICCCA), Greater Noida, India, 2016, pp. 999-1001, doi:

1109/CCAA.2016.7813861.

Jinyuan Wu, Sten Hansen and Zonghan Shi, "ADC and TDC implemented using FPGA," 2007 IEEE Nuclear Science Symposium Conference Record, Honolulu, HI, USA, 2007, pp. 281-286, doi: 10.1109/NSSMIC.2007.4436331.

P. H. W. Leong, "Recent Trends in FPGA Architectures and Applications," 4th IEEE International Symposium on Electronic Design, Test and

Applications (delta 2008), Hong Kong, China, 2008, pp. 137-141, doi:

1109/DELTA.2008.14.

J. E. Istiyanto, "A VHDL-based ADC on FPGA," International Conference on Instrumentation, Communication, Information Technology, and

Biomedical Engineering 2009, Bandung, Indonesia, 2009, pp. 1-3, doi:

1109/ICICI-BME.2009.5417248.

H. Homulle, S. Visser and E. Charbon, "A Cryogenic 1 GSa/s, Soft-Core

FPGA ADC for Quantum Computing Applications," in IEEE Transactions

on Circuits and Systems I: Regular Papers, vol. 63, no. 11, pp. 1854-1865, Nov. 2016, doi: 10.1109/TCSI.2016.2599927.

Bin Le, T. W. Rondeau, J. H. Reed and C. W. Bostian, "Analog-to-digital

converters," in IEEE Signal Processing Magazine, vol. 22, no. 6, pp. 69-77, Nov. 2005, doi: 10.1109/MSP.2005.1550190.

J. -H. Tsai, Y. -J. Chen, M. -H. Shen and P. -C. Huang, "A 1-V, 8b,

MS/s, 113µW charge-recycling SAR ADC with a 14µW asynchronous

controller," 2011 Symposium on VLSI Circuits - Digest of Technical

Papers, Kyoto, Japan, 2011, pp. 264-265.

E. Monmasson, L. Idkhajine and M. W. Naouar, "FPGA-based Controllers," in IEEE Industrial Electronics Magazine, vol. 5, no. 1, pp. 14-26,

March 2011, doi: 10.1109/MIE.2011.940250.

V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas and

J. Craninckx, "An 820W 9b 40MS/s Noise-Tolerant Dynamic-SAR ADC

in 90nm Digital CMOS," 2008 IEEE International Solid-State Circuits

Conference - Digest of Technical Papers, San Francisco, CA, USA, 2008,

pp. 238-610, doi: 10.1109/ISSCC.2008.4523145.

J. Bergeron, "Writing testbenches using SystemVerilog," Springer Science

Business Media, 2013

S. Sutherland, S. Davidmann, and P. Flake, "SystemVerilog for Design

Second Edition: A Guide to Using SystemVerilog for Hardware Design

and Modeling," Springer Science Business Media, 2006

J. Estarán, S. Almonacil et.al "Sub-Baudrate Sampling at DAC and ADC:

Toward 200G per Lane IM/DD Systems," J. Lightwave Technol. 37, 1536-

(2019).

H. -Y. Tai, Y. -S. Hu, H. -W. Chen and H. -S. Chen, "11.2 A

85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm

CMOS," 2014 IEEE International Solid-State Circuits Conference Digest

of Technical Papers (ISSCC), San Francisco, CA, USA, 2014, pp. 196-

, doi: 10.1109/ISSCC.2014.6757397.

Keaveney, Martin and McMahon, Anthony et.al, "The development of

advanced verification environments using system verilog," Institution of

Engineering and Technology,2014.

Downloads

Published

2024-04-19

Issue

Section

ARTICLES / PAPERS / General