Efficient Transient Simulation of Efuse
Abstract
This paper presents a novel approach to model efuse device. An efuse is a simple semiconductor device which can be referred to as a programmable resistor and is available in many modern CMOS technologies. The efuse resistance can be changed by burning procedure, i.e. applying specific electric current value for particular time. The new efuse resistance is retained permanently. The typical efuse application is one-time programmable (OTP) memory. However, process design kits do not provide any model covering the transition from initial to burned state. Thus, verification of programming of an OTP cell is practically impossible. To address this problem, a behavioral Verilog-A model of efuse has been developed. This paper presents the model and its application to verify the example OTP cell designed in 22 nm FD-SOI technology. The proposed model is easy to use and to allow for effective transient simulation of efuse-based designs.
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