Different Generations of FPGA Devices in Implementation of Hash Functions – A Case Study
Abstract
Cryptographic algorithms pose a significant challenge for hardware designers, primarily due to their complex and intentionally irregular internal transformations. These characteristics lead to large, multilayered combinational structures that are difficult to efficiently map onto FPGA architectures. This paper analyzes FPGA implementations of two hash functions: Keccak — the core component of the SHA‑3 algorithm — and BLAKE3. Their performance is evaluated across three generations of AMD devices: 7 Series, UltraScale, and UltraScale+. The study covers both iterative and pipelined variants of the two ciphers, yielding a total of seven distinct hardware realizations. Each module is examined in terms of resource utilization, achievable operating frequency, and dynamic power dissipation across three devices from Kintex families. The use of a unified implementation and evaluation methodology enables a reliable comparison of results, allowing not only to capture the performance and energy‑efficiency benefits offered by newer technologies, but also to identify areas where these advantages become less pronounced for such demanding cryptographic applications.
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