Shared-Semaphored Cache Implementation for Parallel Program Execution in Multi-Core Systems
Abstract
The paper brings forward the idea of multi-threaded
computation synchronization based on the shared semaphored
cache in the multi-core CPUs. It is dedicated to the implementation
of multi-core PLC control, embedded solution or parallel
computation of models described using hardware description languages.
The shared semaphored cache is implemented as guarded
memory cells within a dedicated section of the cache memory that
is shared by multiple cores. This enables the cores to speed up the
data exchange and seamlessly synchronize the computation. The
idea has been verified by creating a multi-core system model using
Verilog HDL. The simulation of task synchronization methods
allows for proving the benefits of shared semaphored memory
cells over standard synchronization methods. The proposed idea
enhances the computation in the algorithms that consist of
relatively short tasks that can be processed in parallel and
requires fast synchronization mechanisms to avoid data race
conditions.
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