Tracing Fault Effects in FPGA Systems

Mariusz Wegrzyn, Janusz Sosnowski


The paper presents the extent of fault effects in FPGA based systems and concentrates on transient faults (induced by single event upsets – SEUs) within the configuration memory of FPGA. An original method of detailed analysis of fault effect propagation is presented. It is targeted at microprocessor based FPGA systems using the developed fault injection technique. The fault injection is performed at HDL description level of the microprocessor using special simulators and developed supplementary programs. The proposed methodology is illustrated for soft PicoBlaze microprocessor running 3 programs. The presented results reveal some problems with fault handling at the software level.


Full Text:



C. Bolchini, A. Miele, and C. Sandionigi, “TMR and partial dynamic reconfiguration to mitigate SEU faults in FPGA,” in IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2007, pp. 87–95.

F. L. Kastensmidt, L. Carro, and R. Reis, Fault-tolerance techniques for SRAM-based FPGAs. Springer, 2006, ISBN-10 0-387-31068-1.

U. Legat, A. Biasizzo, and F. Nowak, “On-line self-recovery of embedded multi-processor SOC on FPGA using dynamic partial reconfiguration,” Information Technology and Control, vol. 41, no. 2, pp. 116–124, 2012.

A. Lesea et al., “The rosetta experiment: atmospheric soft error rate testing in differing technology FPGAs,” IEEE Transactions on Materials Reliability, September 2005.

“Device Reliability Report,” Xilinx Corporation, November 2013, UG 116 (v. 9.6).

Neutron induced Single Event Upsets FAQ, Microsemi 55800021- 0/8.11, August 2011.

Overview of iRoC Technologies Report, “Radiation results of the SER tests of Alcatel FPGA,” December 2005, 55900061-0/8.06.

J. S. Monson, M. Wirthlin, and B. Hutchings, “A fault injection analysis of Linux operating on an FPGA-embedded platform,” International Journal of Reconfigurable Computing, vol. 2012, p. 11, 2012, Article ID 850487, doi:10.1155/2012/850487.

M. Wegrzyn, F. Novak, A. Biasizio, and M. Renovell, “Functional testing of processor cores in FPGA based applications,” Computing and Informatics, vol. 28, no. 1, pp. 97–113, 2009.

P. Gawkowski and J. Sosnowski, “Software implemented fault detection and fault tolerance mechanisms, part II,” Electronics and Telecommunications Quarterly, vol. 51, no. 3, pp. 495–508, 2005.

I. Koren and C. M. Krishna, Fault tolerant systems. Elsevier, Inc., 2007.

A. R. Pandey and H. J. Patel, “Reconfiguration technique for reducing test time and test data volume in Illinois Scan Architecture Based Designs,” in IEEE VLSI Test Symposium, 2002, pp. 9–15.

M. Renovell, J. M. Portal, J. Figueras, and Y. Zorian, “Testing the interconnect of RAM based FPGAs,” IEEE Design and Test of Computers, vol. 15, no. 1, pp. 45–50, 1998.

J. Sosnowski and M. Pawłowski, Universal and application dependent testing of FPGAs, EDCC-2 Companion Workshop on Dependable Computing. AMK Press, 1996, pp. 111–120, ISBN 83-906582-0-8.

M. Rozkovec, J. Jeníˇcek, and O. Novák, “Application dependent FPGA testing method,” in 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, 2010.

J. Sosnowski and M. Pawłowski, “Improving Testability in systems with FPGAs,” in 22nd Euromicro Conference Beyond 2000: Hardware/ Software design Strategies Short Contributions, W. Bob, Ed. IEEE Computer Society Press, 1996, pp. pp. 236–241, ISBN 0-8186-7703-1.

M. B. Tahoori, E. J. McCluskey, M. Renovell, and P. Faure, “A multiconfiguration strategy for an application dependent testing of FPGAs,” in 22nd IEEE VLSI Test Symposium, 2004, pp. 154–159.

G. G. Cieslewski, A. D. George, and A. M. Jacobs, “Acceleration of FPGA fault injection through multi-bit testing,” in Engineering of Reconfigurable systems and Algorithms, July 2010.

S. Rudrakshi, V. Midasala, and S. N. Bhavanam, “Implementation of FPGA based fault injection Tool (FITO) for testing fault tolerant designs,” IACSIT International Journal of Engineering and Technology, vol. 4, no. 5, pp. 522–526, October 2012.

A. Lesea, Continuing experiments of atmospheric neutron effects on deep submicron integrated circuits. Xilinx Corporation, October 2011, WP286.

K. Chapman, SEU strategies for Virtex – 5 devices. Xilinx Corporation, 2010, XAP864 (v.2).

PicoBlaze 8-bit Embedded Microcontroller, “User Guide for Spartan-3, Virtex-II, andVirtex-II Pro FPGAs,” November 21 2005,, 1-800-255-7778 UG129 (v1.1.1).

J. Sosnowski, “Software-based self-testing of microprocessors,” Journal of Systems Architecture, vol. 52, pp. 257–271, 2006.

B. Dutton and C. Stroud, “Soft core embedded processor based built-in self-test of FPGAs,” in 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009.

B. Dutton and C. Stroud, “Built-in self-test of programmable input/output tiles in Virtex-5, FPGAs,” in IEEE Southeastern Symposium on System Theory, 2009, pp. 235–239.

S. K. Venishetti, A. Akoglu, and R. Kalra, “Huerarchical built-in selftesting and FPGA based healing methodology for system on chip,” in IEEE 2nd NASA/ESA Conference on Adaptive Hardware and Systems, 2007.


  • There are currently no refbacks.

International Journal of Electronics and Telecommunications
is a periodical of Electronics and Telecommunications Committee
of Polish Academy of Sciences

eISSN: 2300-1933