A Systematic approach to determining the duty cycle for regenerative comparator used in WSN
Abstract
A low power regenerative comparator is very useful
in Successive Approximation Register (SAR) type Analog to
Digital Converter (ADC) for a Wireless Sensor Node (WSN).
A regenerative type comparator generates output pulses by
comparing input with a reference input. This paper deals with
control of a power with an adjustable duty cycle. The regenerative
comparator with an adjustable duty cycle and a positive feedback
of a latch will help in improving accuracy, speed and also in
achieving the less power consumption. The optimum value of
a duty cycle is determined with taking into consideration of
metastability timing constraints. The proposed low power regenerative
comparator circuit is designed and simulated by using
TSMC 180 nm CMOS technology. The comparator consumes
power as low as 298.54 nW with a regenerative time 264 ps at 1
V power supply.
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