An Efficient Two-phase Clocked Sequential Multiply -Accumulator unit for Image blurring

Authors

  • Rashmi Samanth Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104
  • Subramanya G. Nayak Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104. http://orcid.org/0000-0001-7720-4392

Abstract

The multiply-accumulator (MAC) unit is the basic integral computational block in every digital image and digital signal processor. As the demand grows, it is essential to design these units in an efficient manner to build a successful processor. By considering this into account, a power-efficient, high-speed MAC unit is presented in this paper. The proposed MAC unit is a combination of a two-phase clocked modified sequential multiplier and a carry-save adder (CSA) followed by an accumulator register. A novel two-phase clocked modified sequential multiplier is introduced in the multiplication stage to reduce the power and computation time. For image blurring, these multiplier and adder blocks are subsequently incorporated into the MAC unit. The experimental results demonstrated that the proposed design reduced the power consumption by 52% and improved the computation time by 4% than the conventional architectures. The developed MAC unit is implemented using 180nm standard CMOS technology using CADENCE RTL compiler, synthesized using XILINX ISE and the image blurring effect is analyzed using MATLAB.

Author Biographies

Rashmi Samanth, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104

Presently working as Research scholar in the Department of Electronics & Communication Engineering, Manipal Institute of Technology, Manipal. She received her B.E degree in Electronics & Communication Engineering and the M.Tech degree in Microelectronics from Manipal Institute of Technology, Manipal. Her research interests are in fields of electronics, digital systems, processor architecture and VLSI.

 

Subramanya G. Nayak, Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal-576 104.

Presently working as Professor and Head in the Department of Electronics and Communication Engineering, Manipal Institute of Technology, Manipal. Dr. Nayak has B.E degree in E and C Engineering, M. Tech in Biomedical Engineering and Ph.D., in Electrical and Electronics Engineering with specialization in Pattern Recognition. His research areas of interest are in the field of Processor Architecture design and applications.

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Published

2024-04-19

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Section

Signals, Circuits, Systems