Build Testbenches for Verification in Shift Register ICs using SystemVerilog
Abstract
A testbench is built to verify a functionality of a shift register IC (Integrated Circuit) from stuck-at-faults, stuck-at-1 as well as stuck-at-0. The testbench is supported by components, i.e., generator, interface, driver, monitor, scoreboard, environment, test, and testbench top. The IC consists of sequential logic circuits of D-type flip-flops. The faults may occur at interconnects between the circuits inside the IC. In order to examine the functionality from the faults, both the testbench and the IC are designed using SystemVerilog and simulated using Questasim simulator. Simulation results show the faults may be detected by the testbench. Moreover, the detected faults may be indicated by error statements in transcript results of the simulatorReferences
T. Ndjountche, Digital Electronics 2: Sequential and Arithmetic Logic Circuits. 2016.
G. Nithya and M. Ramaswamy, “Very large scale integrated solution for stuck at faults in synchronous sequential circuits,” J. Comput. Theor. Nanosci., vol. 16, no. 4, 2019, http://doi.org/10.1166/jctn.2019.8047
A. A. Abou-Auf, M. M. Abdel-Aziz, M. A. Abdel-Aziz, and A. A. Ammar, “Fault Modeling and Worst Case Test Vector Generation for Flash-Based FPGAs Exposed to Total Dose,” IEEE Trans. Nucl. Sci., vol. 64, no. 8, 2017, http://doi.org/10.1109/TNS.2017.2687982
D. Addala, P. Teja, and S. Saxena, “Fault simulation algorithm for transistor single stuck short faults,” in Intelligent Circuits and Systems, 2021.
H. M. Gaur, A. K. Singh, and U. Ghanekar, “Design for Stuck-at Fault Testability in Toffoli–Fredkin Reversible Circuits,” Natl. Acad. Sci. Lett., vol. 44, no. 3, 2021, http://doi.org/10.1007/s40009-020-00967-3
P. Wang, A. M. Gharehbaghi, and M. Fujita, “An Automatic Test Pattern Generation Method for Multiple Stuck-At Faults by Incrementally Extending the Test Patterns,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 39, no. 10, 2020, http://doi.org/10.1109/TCAD.2019.2957364
P. Wang, A. M. Gharehbaghi, and M. Fujita, “An Incremental Automatic Test Pattern Generation Method for Multiple Stuck-at Faults,” in Proceedings of the IEEE VLSI Test Symposium, 2019, vol. 2019-April, http://doi.org/10.1109/VTS.2019.8758668
P. Wang, A. M. Gharehbaghi, and M. Fujita, “Automatic Test Pattern Generation for Double Stuck-at Faults Based on Test Patterns of Single Faults,” in Proceedings - International Symposium on Quality Electronic Design, ISQED, 2019, vol. 2019-March,
http://doi.org/10.1109/ISQED.2019.8697831
B. Alizadeh and S. R. Sharafinejad, “Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation,” IEEE Trans. Comput. Des. Integr. Circuits Syst., vol. 38, no. 2, 2019, http://doi.org/10.1109/TCAD.2018.2812123
Y. Ogasahara et al., “Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient
Challenge–Response pair acquisition using Built-In Self-Test before shipping,” Integration, vol. 71, 2020,
http://doi.org/10.1016/j.vlsi.2019.12.002
V. Shivakumar, C. Senthilpari, and Z. Yusoff, “A Low-Power and Area-Efficient Design of a Weighted Pseudorandom Test-Pattern Generator for a Test-Per-Scan Built-in Self-Test Architecture,” IEEE Access, vol. 9, 2021, http://doi.org/10.1109/ACCESS.2021.3059171
M. Sharma and J. Dhanoa, “Smart Logic Built in Self-Test in SOC,” 2020, http://doi.org/10.1109/ICRAIE51050.2020.9358296
Widianto, “A SIGNATURE REGISTER OF A BIST TO DETECT STUCK-AT-FAULTS IN COMBINATIONAL LOGIC ICS,” in SENTRA, 2020, pp. 39–44,
http://doi.org/https://doi.org/10.22219/sentra.v0i6.3811
T. D. Prasad and B. R. Babu, “Design and Simulation of SPI Master / Slave Using Verilog HDL,” Int. J. Sci. Res., vol. 3, no. 8, 2014.
P. Flake, P. Moorby, S. Golson, A. Salz, and S. Davidmann, “Verilog HDL and its ancestors and descendants,” Proc. ACM Program. Lang., vol. 4, no. HOPL, 2020, http://doi.org/10.1145/3386337
M. Qiu, S. Yu, Y. Wen, J. Lü, J. He, and Z. Lin, “Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control,” Int. J. Bifurc. Chaos, vol. 27, no. 3, 2017,
http://doi.org/10.1142/S0218127417500407
M. W. Anwar, M. Rashid, F. Azam, and M. Kashif, “Model-based design verification for embedded systems through SVOCL: an OCL extension for SystemVerilog,” Des. Autom. Embed. Syst., vol. 21, no. 1, 2017, http://doi.org/10.1007/s10617-017-9182-z
K. K. Yadu and R. Bhakthavatchalu, “Block Level SoC Verification Using Systemverilog,” 2019, http://doi.org/10.1109/ICECA.2019.8821909
M. W. Anwar, M. Rashid, F. Azam, M. Kashif, and W. H. Butt, “A model-driven framework for design and verification of embedded systems through SystemVerilog,” Des. Autom. Embed. Syst., vol. 23, no. 3–4, 2019, http://doi.org/10.1007/s10617-019-09229-y
A. A. Vivekananda and E. Enoiu, “Automated test case generation for digital system designs: A mapping study on vhdl, verilog, and systemverilog description languages,” Designs, vol. 4, no. 3, 2020, http://doi.org/10.3390/designs4030031
“Design and Verification of UART using System Verilog,” Int. J. Eng. Adv. Technol., vol. 9, no. 5, 2020,
http://doi.org/10.35940/ijeat.e1135.069520
K. Benefits, “Industry’s Highest Performance Simulation Solution,” Synopsys, 2020.
L. A. Kadlubowski and P. Kmon, “Test and Verification Environment and Methodology for Vernier Time-to-Digital Converter Pixel Array,” 2021, http://doi.org/10.1109/DDECS52668.2021.9417054
D. Ahlawat and N. Kr. Shukla, “Performance Analysis of Verilog Directed Testbench vs Constrained Random SystemVerilog Testbench,” Int. J. Comput. Appl., vol. 118, no. 22, 2015, http://doi.org/10.5120/20874-3612
B. Chinna Munaiah and S. M. Shamsheer Daula, “Design and verification of advanced high-performance bus lite protocol using questa sim,” J. Adv. Res. Dyn. Control Syst., vol. 11, no. 9 Special Issue, 2019, http://doi.org/10.5373/JARDCS/V11/20192572
Downloads
Published
Issue
Section
License
Copyright (c) 2022 International Journal of Electronics and Telecommunications
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
1. License
The non-commercial use of the article will be governed by the Creative Commons Attribution license as currently displayed on https://creativecommons.org/licenses/by/4.0/.
2. Author’s Warranties
The author warrants that the article is original, written by stated author/s, has not been published before, contains no unlawful statements, does not infringe the rights of others, is subject to copyright that is vested exclusively in the author and free of any third party rights, and that any necessary written permissions to quote from other sources have been obtained by the author/s. The undersigned also warrants that the manuscript (or its essential substance) has not been published other than as an abstract or doctorate thesis and has not been submitted for consideration elsewhere, for print, electronic or digital publication.
3. User Rights
Under the Creative Commons Attribution license, the author(s) and users are free to share (copy, distribute and transmit the contribution) under the following conditions: 1. they must attribute the contribution in the manner specified by the author or licensor, 2. they may alter, transform, or build upon this work, 3. they may use this contribution for commercial purposes.
4. Rights of Authors
Authors retain the following rights:
- copyright, and other proprietary rights relating to the article, such as patent rights,
- the right to use the substance of the article in own future works, including lectures and books,
- the right to reproduce the article for own purposes, provided the copies are not offered for sale,
- the right to self-archive the article
- the right to supervision over the integrity of the content of the work and its fair use.
5. Co-Authorship
If the article was prepared jointly with other authors, the signatory of this form warrants that he/she has been authorized by all co-authors to sign this agreement on their behalf, and agrees to inform his/her co-authors of the terms of this agreement.
6. Termination
This agreement can be terminated by the author or the Journal Owner upon two months’ notice where the other party has materially breached this agreement and failed to remedy such breach within a month of being given the terminating party’s notice requesting such breach to be remedied. No breach or violation of this agreement will cause this agreement or any license granted in it to terminate automatically or affect the definition of the Journal Owner. The author and the Journal Owner may agree to terminate this agreement at any time. This agreement or any license granted in it cannot be terminated otherwise than in accordance with this section 6. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.
7. Royalties
This agreement entitles the author to no royalties or other fees. To such extent as legally permissible, the author waives his or her right to collect royalties relative to the article in respect of any use of the article by the Journal Owner or its sublicensee.
8. Miscellaneous
The Journal Owner will publish the article (or have it published) in the Journal if the article’s editorial process is successfully completed and the Journal Owner or its sublicensee has become obligated to have the article published. Where such obligation depends on the payment of a fee, it shall not be deemed to exist until such time as that fee is paid. The Journal Owner may conform the article to a style of punctuation, spelling, capitalization and usage that it deems appropriate. The Journal Owner will be allowed to sublicense the rights that are licensed to it under this agreement. This agreement will be governed by the laws of Poland.
By signing this License, Author(s) warrant(s) that they have the full power to enter into this agreement. This License shall remain in effect throughout the term of copyright in the Work and may not be revoked without the express written consent of both parties.