Reducing Power of BLAKE3 Implementations with Dedicated FPGA Resources
Abstract
The BLAKE cryptographic hash functions are efficiently expressed in software; however, their hardware implementations do not match the speed and power efficiency of alternative methods. This paper assesses a possible method of decreasing power consumption in BLAKE3 FPGA implementations by application of dedicated DSP resources for binary summations in place of standard adders realized in logic cells within the programmable array. The analysis considers various viable configurations of cipher realization: from the standard iterative architecture (featuring one round instance in hardware), to organizations with 2, 4, and 6-stage pipelining employed for high processing efficiency. The power results are generated by simulating operation of the designs after their full implementation in a Spartan-7 device. Substituting the standard adders configured in programmable fabric with 7 series DSP48E1 elements can significantly decrease the high dynamic power consumption that adversely affected the standard non-pipelined BLAKE3 implementation, but can also bring some disadvantages with regard to hardware size or speed. Moreover, it does not offer any improvement in highly pipelined architectures. In addition to exploring one approach for reducing power consumption of this particular cipher, the paper can also serve as another case study on improving FPGA implementation by leveraging specialized resources that would otherwise remain unused but are available in the used device.
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